update 20180819: add experiments and start with regulation
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@ -1,4 +1,5 @@
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import matplotlib.pyplot as plt
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import matplotlib.cm as cm
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import numpy as np
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import wafer
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import VisTools.plotting as vtp
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@ -9,6 +10,40 @@ plt.rcParams['axes.facecolor'] = 'white'
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plt.figure(figsize=(8, 4))
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def gen_reg_theory():
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xdata = np.linspace(0, 150, 1001)
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# consts
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rpar = 75000
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rser = 9400
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r0 = 1.0029e-3
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r1 = 15.966e-3
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iret = 9.1
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plt.clf()
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plt.figure(figsize=(8, 4))
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for n, voff in enumerate([1.75, 1.8, 1.85, 1.9]):
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ydata = iret * r1 + r0 * xdata + voff
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ydata = (.7*30100 / (ydata - .7)) - 6490 - rser
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ydata = rpar * ydata / (rpar + ydata) * 256 / 10000
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plt.plot(
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[x for x, y in zip(xdata, ydata) if y >= 0],
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[y for y in ydata if y >= 0],
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color=f"C{n}",
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label=f"V$_{{off}}$ = {voff}"
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)
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plt.plot(
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xdata,
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ydata,
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color=f"C{n}",
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linestyle='dotted'
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)
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plt.legend()
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plt.savefig('reg.pdf')
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def gen_reticle_empty():
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plt.clf()
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@ -20,6 +55,37 @@ def gen_reticle_empty():
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ax.set_aspect("equal")
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plt.savefig('wafer.pdf')
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def gen_reticle_patterns():
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plt.clf()
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f, sax = plt.subplots(2, 2, figsize=(8, 6))
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sax = np.resize(sax, 4)
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patterns = [
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[0, 2, 8, 10, 12, 14, 25, 27, 29, 31, 41, 43],
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[1, 9, 11, 13, 24, 26, 28, 30, 32, 40, 42, 44],
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[3, 5, 7, 15, 17, 19, 21, 23, 34, 36, 38, 46],
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[4, 6, 16, 18, 20, 22, 33, 35, 37, 39, 45, 47]
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]
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for ax, p in zip(sax, patterns):
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w = wafer.WaferRepr()
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for r in p:
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w.set(r, .2)
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w.placeim(ax, (0, 0), cmap=cm.tab20c, nonumber=True)
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ax.set_ylim([-.6, 7.6])
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ax.set_xlim([-.6, 8.6])
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ax.set_aspect('equal')
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ax.axis('off')
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ax.invert_yaxis()
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plt.tight_layout()
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plt.savefig('wpattern.pdf')
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def gen_48v_theory():
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xdata = np.linspace(43, 53, 100)
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@ -58,9 +124,13 @@ def gen_1v8_theory():
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plt.clf()
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plt.plot(xdata, ydata, label="Equation after Datasheet")
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vps = vtp.fit(xdata, ydata, lambda x,m,p,a,c: a/(m*x-p)+c, [.1, -1, 1, 1.5])
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vps = vtp.fit(
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xdata,
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ydata,
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lambda x, m, p, a, c: a/(m*x-p)+c, [.1, -1, 1, 1.5]
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)
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#plt.plot(xdata, vps[2].n / (vps[0].n * xdata - vps[1].n) + vps[3].n)
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# plt.plot(xdata, vps[2].n / (vps[0].n * xdata - vps[1].n) + vps[3].n)
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vtt.unc_tolatex(vps[0], None, 'theo.tex', name="m")
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vtt.unc_tolatex(vps[1], None, 'theo.tex', name="p")
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vtt.unc_tolatex(vps[2], None, 'theo.tex', name="a")
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@ -77,3 +147,5 @@ if __name__ == "__main__":
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gen_48i_theory()
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gen_1v8_theory()
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gen_reticle_empty()
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gen_reg_theory()
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gen_reticle_patterns()
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@ -67,7 +67,7 @@ The first experiments to run are the caracterization of hardware behavior. These
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\label{v10_precalib}
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\end{figure}
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The 9.6V Calibration, in contrast, shows only a slight deviation of the internal values and the reference measurement, which results in a list of coefficients (\autoref{pitdb}, line 7), very similar to those set in the theoretical defaults.
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The 9.6V Calibration, in contrast, shows only a slight deviation of the internal values and the reference measurement, which results in a list of coefficients (\autoref{}, line 7), very similar to those set in the theoretical defaults.
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This small difference is explained by the simple voltage division used as our circuitry, and no amplification, as for the input voltage circuit.
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@ -119,11 +119,6 @@ Note that the 9.6V Output does in fact not have a include circuit for measuring
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%\section{after Calibration}
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%\minty[minted options={lastline=10}, label={pitdb}]{yaml}{./pitstop/pitdb.yaml}
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%\subsection{Voltages}
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% \subsubsection{48V Input}
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% \subsubsection{9.6V Output}
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@ -132,85 +127,140 @@ Note that the 9.6V Output does in fact not have a include circuit for measuring
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%\subsection{Currents}
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% \subsubsection{48V Input}
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% \subsubsection{9.6V Output}
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% \subsubsection{1.8V Output}
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% \begin{figure}[H]
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% \centering
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% \hspace*{-.16\columnwidth}
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% \includegraphics[width=1.3\columnwidth]{./pitstop/20180702/i18ana_postcalib.pdf}
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% \caption{Post Calibration Measurement of Output Current at the 1.8V Analog Terminal (29.06.2018}
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% \label{postcalib18iana}
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% \centering
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% \hspace*{-.16\columnwidth}
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% \includegraphics[width=1.3\columnwidth]{./pitstop/20180702/i18ana_postcalib.pdf}
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% \caption{Post Calibration Measurement of Output Current at the 1.8V Analog Terminal (29.06.2018}
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% \label{postcalib18iana}
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% \end{figure}
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\section{1.8V Regulation}
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As Described beforehand the Output Voltages for both analog and digital can be adjusted to some degree and therefore we can compensate for the dropoff occuring between PowerIt Output Terminals and Reticles.
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\begin{figure}[H]
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\centering
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\includegraphics[width=\columnwidth]{./data/theory/wpattern.pdf}
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\caption{Used regular patterns for current tests on PowerWafer}%
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\label{fig:wpattern}
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\end{figure}
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\subsection{Characterization of Dropoff}
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Wanting to observe and characterize the voltage drop, first the connections between PowerIt and Reticles can be measured with the in \autoref{fig:retmodel} described connections, which in actuallity are the PowerIT Terminal and corresponding analog readout pin on a Analog readout board.
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IN \autoref{1v8dip} a single reticles Voltage Dip for different Current Draws is visualized.
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A relatively linear trand and residuals of a trigonometric behavior can be observed, most likely the result of the inaccurately measureable currrent which is in this Figure done inside the PowerIt.
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To use the PowerWfer for testing one of the patterns in \autoref{fig:wpattern} will be used, each pattern has a aproximate currentdraw of 120A and will distribute heat and draw per terminal evenly.
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In \autoref{1v8dip} a single reticles (40) Voltage Dip for different Current Draws is visualized.
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A relatively linear trend and residuals of a trigonometric behavior can be observed (most likely the result of the inaccurately measureable current draw, which here is done inside the PowerIt).
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\begin{figure}[H]
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\centering
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%\vspace*{-1cm}
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\hspace*{-.16\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./pitstop/20180807/ret_vdip.pdf}
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\caption{Voltage dip observed between PowerIt and HICANN, each point represents the state after enabling additional Reticles on the PowerWafer ()}
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\caption{Voltage dip observed between PowerIt and HICANN, each point represents a state after enabling additional Reticles on the PowerWafer (right upper wafer in \autoref{fig:wpattern})}
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\label{1v8dip}
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\end{figure}
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This measuring circuit has some inconsitencies because of the 2nd degree polynimial fit, which is not the appropriate description fr the used compenents, but intead should be some function proportional to $\frac 1x$, like the one described in \autoref{eq:fullreg}.
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\subsection{after Numerical-Correction}
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Here a Voltage Drop vs. Current draw of the wafer shows a linear behavior and therefore can be regulated on basis of the current measurement done by on board Measurement circuit.
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The initial approach is a numerical. Through derivation from Figures~\ref{1v8dip} and~\ref{v18_precalib} we can plot a function which maps the measured output current to a corresponding potentiometer setting (\autoref{numericalreg}) for which the observed dropoff will be mitigated (or at least near that). Also important is that it is not possible to use non interger values for the potentiometer setting.
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\subsection{Numerical-Correction (Regulation)}
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The initial idea, to approach the correction of this dropoff is a Numerical: the SWRM (\autoref{sec:swrm}) and its corresponding Equations can be applied here.
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\autoref{eq:fullreg}, which maps the measured output current to a corresponding potentiometer setting, requires the Dropoff to be linear, which was observed.
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To apply this approach, two assumptions need to be made:
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\begin{itemize}
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\item all reticles have the same current draw (already nmot accurate, see \autoref{1v8dip})
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\item all reticles experience the same Voltage Dip (as observed for Reticle 40)
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\end{itemize}
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and the following four values are required, before a regulation can be attempted:
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\begin{itemize}
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\item \(I_{ret}\), the current draw of a single reticle,
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\item \(R_0\), the Resistance between PowerIt and FET,
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\item \(R_1\), the Resstance of a single Reticle
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\item \(V_{off}\), the wanted Voltage at a Reticle
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\end{itemize}
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\subsubsection{\(V_{off}\)}
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This Value is the wanted settable, value which should be delivered to each Reticle.
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\subsubsection{\(I_{ret}\)}
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\begin{figure}[H]
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\centering
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\hspace*{-.16\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./pitstop/20180807/ret_regulation.pdf}
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\caption{Potentiometer Setting (discrete integer), derived from ouput current (discrete floating point). }
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\label{numericalreg}
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\vspace{-1cm}
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\hspace*{-.15\columnwidth}
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\includegraphics[width=1.3\columnwidth]{../pitstop/20180819/reticle_ihist.pdf}
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\caption{Distribution of analog current draw for all reticles on the PowerWafer (which were possible to measure \(\rightarrow\) \autoref{sec:pitfalls})}%
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\label{fig:ihist}
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\end{figure}
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Fitting these values, with a polynomial of 2nd degree, we obtain:
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\begin{align}
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P_{val} =& \lfloor m_2 \cdot I_{ana}^2 + m_1 \cdot I_{ana} + m_0 \rceil\\
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m_2 =& 51.390262 \frac 1 A\\
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m_1 =& -0.263850\frac 1 A\nonumber\\
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m_0 =& 0.000258\frac 1 A\nonumber
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\end{align}
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To get a representative value for use in the SWRM, the mean of all reticles current draw was taken:
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\begin{align}
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\pyval{iretmeancorr}
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\end{align}
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Which is the numeraical solution if the only desired voltage on HICAN Chips is 1.8V. But if we want to change these, we need a more general solution.
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\subsubsection{\(R_1\)}
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This Resistace can be obtained through extrapolating the observed voltage dip to 0 (using \autoref{eq:voff}, and the now obtained \(I_{ret}\)).
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Assuming the 2nd order Term to be small enough, we can assume a linear proportionality between the current and voltage:
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\begin{align}
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V_O(0) =& I_{ret} \cdot R_1\nonumber\\
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R_1 =& \SI{7.2357+-0.4417}{\milli\ohm}
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\end{align}
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\begin{align}
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I_{ana, eff} = I_{ana} - \frac{V_{out}-1.8V}{c}
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\end{align}
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where c is obtained from the linear fit (incline) in figure \ref{1v8dip}
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\begin{align}
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c = 71.6978\cdot 10^{-3} \frac V A
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\end{align}
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%\begin{figure}[H]
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% \centering
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% \hspace*{-.16\columnwidth}
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% \includegraphics[width=1.3\columnwidth]{./pitstop/20180807/ret_regulation.pdf}
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% \caption{Potentiometer Setting (discrete integer), derived from ouput current (discrete floating point). }
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% \label{numericalreg}
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%\end{figure}
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%Fitting these values, with a polynomial of 2nd degree, we obtain:
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%\begin{align}
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% P_{val} =& \lfloor m_2 \cdot I_{ana}^2 + m_1 \cdot I_{ana} + m_0 \rceil\\
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% m_2 =& 51.390262 \frac 1 A\\
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% m_1 =& -0.263850\frac 1 A\nonumber\\
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% m_0 =& 0.000258\frac 1 A\nonumber
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%\end{align}
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%Which is the numeraical solution if the only desired voltage on HICAN Chips is 1.8V. But if we want to change these, we need a more general solution.
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%Assuming the 2nd order Term to be small enough, we can assume a linear proportionality between the current and voltage:
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%
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%\begin{align}
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%I_{ana, eff} = I_{ana} - \frac{V_{out}-1.8V}{c}
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%\end{align}
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%
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%where c is obtained from the linear fit (incline) in figure \ref{1v8dip}
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%\begin{align}
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% c = 71.6978\cdot 10^{-3} \frac V A
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%\end{align}
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\begin{figure}[H]
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\centering
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\hspace*{-.1\columnwidth}
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\includegraphics[width=1.2\columnwidth]{./pitstop/20180807/reticle_pic}
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\caption{ret5wafer}
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\includegraphics[width=1.2\columnwidth]{../pitstop/processing/neighborhoood_5.pdf}
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\caption{ret5wafer}%
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\label{fig:wafer-ret5}
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\end{figure}
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\begin{figure}[H]
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\centering
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\hspace*{-.15\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./pitstop/20180807/reticle_corr}
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\caption{ret5}
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\caption{ret5}%
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\label{fig:ret5}
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\end{figure}
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@ -228,5 +278,5 @@ where c is obtained from the linear fit (incline) in figure \ref{1v8dip}
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\pyval{r1meancorr}
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\end{align}
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\section{Pitfalls}
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\section{Pitfalls} \label{sec:pitfalls}
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@ -2,9 +2,7 @@
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\chapter{Results}
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This Chapter summaizes all of the resulting Workflow that has been developed during this Bachelor Thesis Work.
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Mainly the Firmware Changes compared to the state at wich it was left off after the previously taken Internship \cite{
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% TODO: insert ubib ref to Internship report
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}
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Mainly the Firmware Changes compared to the state at wich it was left off after the previously taken Internship \cite{poweritupgrade}
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\section{Firmware}
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@ -52,9 +50,13 @@ An example entry for each PowerIt entry looks like figure \ref{pitdb-example}
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poly18v: [0.0, 1.0, 0.0]
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poly48v: [0.0, 27.386, 0.0]
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\end{mintyfig}%
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\end{mintyfig}
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\end{figure}
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\begin{figure}
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\centering
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\minty[minted options={lastline=10}, label=pitdb]{yaml}{pitstop/pitdb.yaml}
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\end{figure}
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\subsection{How to calibrate a PowerIt Board}
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@ -77,7 +79,7 @@ Using the script any one of the following Values can be tested and calibrated:
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The simplest way to setup your environment consists of cloning the PItSTOP Project onto your Client:
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\begin{mintylst}{bash}
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$ git clone https://url.to.pitstop
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> git clone https://url.to.pitstop
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\end{mintylst}
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then substituting the \verb|rsync| target:
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@ -93,11 +95,11 @@ Runnig the test requires the following commands
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\\
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Serverside:
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\begin{mintylst}{bash}
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$ python server.py
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> python server.py
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\end{mintylst}
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Clientside:
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\begin{mintylst}{bash}
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$ python aggregator.py
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> python aggregator.py
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\end{mintylst}
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Now just following the instructions given, the selected test can be run:
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\begin{mintylst}{text}
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@ -114,3 +116,11 @@ Now just following the instructions given, the selected test can be run:
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\section{Regulation}
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\begin{figure}[H]
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\centering
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\hspace*{-.17\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./data/theory/reg.pdf}
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\caption{theretical potentiomete settings for meausured current }%
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\label{fig:regtheo}
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\end{figure}
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@ -22,7 +22,10 @@ The circuits for measuring input Voltage and current are the most complex, becau
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\item amplify the voltage, to be in the Chips Voltage range of 0--3.3V
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\end{itemize}
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The already implemented Cicuit can be seen in \autoref{mon48v}. It consists of a 1:240 Voltage Divider, a full differential isolation amplifier taking in the $\approx$ 200mV (nominal voltage range), and amplifying it by a factor of 8 ($r_\text{diffOpAmp}$~\cite{diffopamp}). It is also decoupling the input and output voltages, so our 48V and 3.3V circuit parts are electricly insulated. The remaining operational amplifier provides futher amplification by a factor of 1.1 ($r_\text{OpAmp}$)
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The already implemented Cicuit can be seen in \autoref{mon48v}.
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It consists of a 1:240 Voltage Divider, a full differential isolation amplifier taking in the \(\approx\) 200mV (nominal voltage range), and amplifying it by a factor of 8 (\(r_\text{diffOpAmp}\)~\cite{diffopamp}).
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It is also decoupling the input and output voltages, so our 48V and 3.3V circuit parts are electricly insulated.
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The remaining operational amplifier provides futher amplification by a factor of 1.1 (\(r_\text{OpAmp}\))
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This circuit results in the following equation for calculating the input voltage from a pin voltage:
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@ -172,7 +175,7 @@ Each Reticle is connected to its corresponding CURE Board, which can read voltag
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Another specialization of the Power wafer is, that all reticles voltages are connected directly to pins on the Analog Readout Boards~\cite{anabpower}. There it is possible to measure a voltage, which is the one after the load resistors in \autoref{fig:retmodel}
|
||||
|
||||
\subsection{Simple Wafer Resistance Model (SWRM)}
|
||||
\subsection{Simple Wafer Resistance Model (SWRM)}\label{sec:swrm}
|
||||
|
||||
The circuit in \autoref{fig:retmodel} can be used, as a first step, to describe the connections powering Reticles inside a wafer.
|
||||
|
||||
|
|
@ -215,7 +218,6 @@ inside the code used for Regulation, \autoref{eq:fullreg} will be used to create
|
|||
\Rightarrow V_O =& I_{ret} \cdot \left( R_1 + R_0 \cdot n_{ret} \right) + V{off}\label{eq:vout2}
|
||||
\end{align}
|
||||
|
||||
|
||||
\subsection{Distance Wafer Resistance Model}
|
||||
|
||||
Although the through SWRM gained functions are useful for determinig a theoretical Regulation procedure, it is still not near the realworld scenario.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
\ExplSyntaxOn
|
||||
\newcommand{\pyval}[1]{%
|
||||
\str_case:nn{#1}{%
|
||||
{ 0 }{ m = \SI{-1.6911+-0.0000}{ }}
|
||||
{ 1 }{ p = \SI{567.6618+-0.0000}{ }}
|
||||
{ 2 }{ a = \SI{-621.1199+-0.0000}{ }}
|
||||
{ 3 }{ c = \SI{0.9318+-0.0000}{ }}
|
||||
}
|
||||
}
|
||||
\ExplSyntaxOff
|
||||
BIN
thesis.pdf
BIN
thesis.pdf
Binary file not shown.
|
|
@ -3,7 +3,7 @@
|
|||
\usepackage{xparse}
|
||||
\usepackage{siunitx}
|
||||
\sisetup{separate-uncertainty}
|
||||
\input{./pitstop/20180807/res.tex}
|
||||
\input{../pitstop/20180819/res.tex}
|
||||
|
||||
\usepackage{fontawesome}
|
||||
\pretitle{\centering \huge \bfseries }
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
To reduce the eroneous data created within BarainScaleS, the PowerIt Board, one of its submodules, was upgraded and received a software ovehaul, containing calibration for the on board measurements and regultion capability for its most critical output terminal.
|
||||
\\\\
|
||||
|
||||
Monitoring System Status und Regulations Parameter innherhalb eines komplexen Systems, wie etwa BrainScaleS, entahlten kritische Punkte des Systems, welche im Flalle eines Fehlers in Promblemen mit dem kompletten System resultieren können. Um die innerhalb von BrainScales erzeugten fehlerhaften Daten zu reduzieren, hat das PowerIt Submodul ein Firmware Upgrade erhalten, diese enthält nun Kalibrationen für die Board eigenen Messungen, sowie die Fähigkeit die Systemkritischen Ausgänge zu regulieren.
|
||||
Monitoring System Status und Regulations Parameter innerhalb eines komplexen Systems, wie etwa BrainScaleS, entahlten kritische Punkte des Systems, welche im Flalle eines Fehlers in Promblemen mit dem kompletten System resultieren können. Um die innerhalb von BrainScales erzeugten fehlerhaften Daten zu reduzieren, hat das PowerIt Submodul ein Firmware Upgrade erhalten, diese enthält nun Kalibrationen für die Board eigenen Messungen, sowie die Fähigkeit die Systemkritischen Ausgänge zu regulieren.
|
||||
\end{abstract}
|
||||
|
||||
\setcounter{tocdepth}{1}
|
||||
|
|
|
|||
Loading…
Reference in New Issue