From 1a851697b79169f8ca2bd4b5da92832c2af45a3d Mon Sep 17 00:00:00 2001 From: acereca Date: Fri, 27 Jul 2018 15:12:32 +0200 Subject: [PATCH] update 20180727 --- data/m03_poticalib/recalc.py | 74 +++++++++++++++++++++++++++++++ parts/experiments.tex | 46 +++++++++++++++++++- parts/theory.tex | 23 ++++++++++ tabs/registerbuffer.tex | 37 ++++++++-------- thesis.tex | 2 +- tikz/reticlepower.pdf | Bin 0 -> 1227 bytes tikz/reticlepower.svg | 75 ++++++++++++++++++++++++++++++++ tikz/reticlepower.synctex(busy) | 0 tikz/reticlepower.tex | 14 ++++++ 9 files changed, 250 insertions(+), 21 deletions(-) create mode 100644 data/m03_poticalib/recalc.py create mode 100644 tikz/reticlepower.pdf create mode 100644 tikz/reticlepower.svg create mode 100644 tikz/reticlepower.synctex(busy) create mode 100644 tikz/reticlepower.tex diff --git a/data/m03_poticalib/recalc.py b/data/m03_poticalib/recalc.py new file mode 100644 index 0000000..cafc38d --- /dev/null +++ b/data/m03_poticalib/recalc.py @@ -0,0 +1,74 @@ +#! python3 +import pandas as pd +import matplotlib.pyplot as plt + +import VisTools.plotting as vp +import ruamel.yaml + +yaml = ruamel.yaml.YAML() + +data = pd.read_csv('./log_poticalib_ana_02.csv') + +print(data.columns) + +data['val_poti'] = [int(i, 16) for i in data['val_poti']] + +def poll_db(uuid: str): + + db = [] + with open("./pitstop/pitdb.yaml") as f: + db_raw = yaml.load_all(f) + + for doc in db_raw: + db.append(doc) + + for doc in db: + doc = dict(doc) + if doc['id'] == uuid: + return doc + return None + +def __calc_vpin(data: pd.DataFrame, poly): + m = poly + + if m[2] != 0: + data['x'] = 4 * m[2] * (data['v_pit/v'] - m[0]) + m[1]**2 + data['x'] = np.sqrt(data['x'].tolist()) + data['x'] -= m[1] + data['x'] /= (2 * m[2]) + else: + data['x'] = (data['v_pit/v'] - m[0]) / m[1] + + return data + +default = poll_db('default') + +data = __calc_vpin(data, default['poly18v']) + +plt.errorbar( + data['x'], + data['v_pit/v'], + fmt='.' +) + +plt.errorbar( + data['x'], + data['v_keith/v'], + fmt='.' +) + +res = vp.fit( + data['x'], + data['v_keith/v'], + lambda x,m0,m1,m2: m0+m1*x+m2*x*x, + default['poly18v'] +) + +plt.plot( + data['x'], + [res[0].n+e*res[1].n+res[2].n*e*e for e in data['x']] +) + +print('poly18v:',[round(e.n,4) for e in res]) +plt.show() + diff --git a/parts/experiments.tex b/parts/experiments.tex index 3452ae5..f42236b 100644 --- a/parts/experiments.tex +++ b/parts/experiments.tex @@ -156,7 +156,7 @@ The secondary plots confirm the \begin{figure}[H] \centering \hspace*{-.16\columnwidth} - \includegraphics[width=1.3\columnwidth]{pitstop/20180629/i18ana_postcalib.pdf} + \includegraphics[width=1.3\columnwidth]{../pitstop/20180702/i18ana_postcalib.pdf} \caption{Post Calibration Measurement of Output Current at the 1.8V Analog Terminal (29.06.2018} \label{postcalib18iana} \end{figure} @@ -165,7 +165,49 @@ The secondary plots confirm the \subsection{Characterization of Dropoff} -\subsection{after -Correction} +Wanting to observe and characterize the voltage drop, happening between the PowerIt output terminal and the HICANN Chips, first the in figure \ref{1v8dip} monitored behavior can be seen. + +\begin{figure}[H] + \centering + \hspace*{-.16\columnwidth} + \includegraphics[width=1.3\columnwidth]{../pitstop/20180727/ret_vdip.pdf} + \caption{Voltage dip observed between PowerIt and HICANN, each point represents the state after enabling additional Reticles on the PowerWafer} + \label{1v8dip} +\end{figure} + +\subsection{after Numerical-Correction} + +The initial approach is a numerical. Through derivation from figures \ref{1v8dip} and \ref{v18_precalib} we can plot a function which maps the measured output current to a corresponding potentiometer setting (fig. \ref{numericalreg}) for which the observed dropoff will be mitigated (or at least near that). Also important is that it is not possible to use non interger values for the potentiometer setting. + +\begin{figure}[H] + \centering + \hspace*{-.16\columnwidth} + \includegraphics[width=1.3\columnwidth]{../pitstop/20180727/ret_regulation.pdf} + \caption{Potentiometer Setting (discrete integer), derived from ouput current (discrete floating point). } + \label{numericalreg} +\end{figure} + +Fitting these values, with a polynomial of 2nd degree, we obtain: +\begin{align} + P_{val} =& \lfloor m_2 \cdot I_{ana}^2 + m_1 \cdot I_{ana} + m_0 \rceil\\ + m_2 =& 51.390262 \frac 1 A\\ + m_1 =& -0.263850\frac 1 A\nonumber\\ + m_0 =& 0.000258\frac 1 A\nonumber +\end{align} + +Which is the numeraical solution if the only desired voltage on HICAN Chips is 1.8V. But if we want to change these, we need a more general solution. + +Assuming the 2nd order Term to be small enough, we can assume a linear proportionality between the current and voltage: + +\begin{align} +I_{ana, eff} = I_{ana} - \frac{V_{out}-1.8V}{c} +\end{align} + +where c is obtained from the linear fit (incline) in figure \ref{1v8dip} + +\begin{align} + c = 71.6978\cdot 10^{-3} \frac V A +\end{align} \section{Pitfalls} diff --git a/parts/theory.tex b/parts/theory.tex index 1ae5ffd..a987a74 100644 --- a/parts/theory.tex +++ b/parts/theory.tex @@ -106,3 +106,26 @@ While the measurements done by the STM32-Chip are using a 12bit ADC, we don't ha \section{1.8V Output Regulation} %\section{Firmware Requirements} + +\section{Power Wafer} +To test the 1.8V Regulation the so called Power Wafer is going to be used, it bahves similarly to a in BrainScales used "fuctional" Wafer module. But it is fundamentally different, as it cannot be used for computation, but only to test for voltages and currents. Its internals behave like switchable ohmic resistors, which provides us with a macimum power draw per section (Reticle) of what is allowed inside a usable wafer. + +Like its counterparts, it has the same Layout + +\begin{figure}[H] + \centering + \includegraphics[width=\columnwidth]{../pitstop/20180727/ret_pic.pdf} + \caption{example diagram of power wafer, 16 Reticles in use} +\end{figure} + +and each of the 48 Reticles can be accessed, digitaly as well as electricaly. + +For this work the following circuit can be used to describe the connections, powering these Reticles. + +\begin{figure}[H] + \centering + %TODO: unclude simplified resistor ladder + \includegraphics[width=1.3\paperwidth]{<`4`>} + \caption{<`5`>} + \label{<`6`>} +\end{figure} diff --git a/tabs/registerbuffer.tex b/tabs/registerbuffer.tex index a79286c..3c3ee44 100644 --- a/tabs/registerbuffer.tex +++ b/tabs/registerbuffer.tex @@ -18,26 +18,27 @@ 0x42 & polyFit.T & float arr & 12 & rw\\ \hline 0x4e & sampleTicks & byte & 1 & rw\\ + 0x4f & V\_out & float & 4 & rw\\ \hline - 0x4f & TEMP\_SENSOR & float & 4 & r\\ - 0x53 & EXT\_AIN & float & 4 & r\\ - 0x57 & MONITOR\_48V & float & 4 & r\\ - 0x5b & MONITOR\_48I & float & 4 & r\\ - 0x5f & MONITOR\_8VBUS & float & 4 & r\\ - 0x63 & MONITOR\_8IBUS & float & 4 & r\\ - 0x67 & MONITOR\_8V\_0 & float & 4 & r\\ - 0x6b & MONITOR\_8V\_1 & float & 4 & r\\ - 0x6f & MONITOR\_8V\_2 & float & 4 & r\\ - 0x73 & MONITOR\_8V\_3 & float & 4 & r\\ - 0x77 & VDD\_1V8\_ANA & float & 4 & r\\ - 0x7b & VDD\_1V8\_IOUT\_ANA & float & 4 & r\\ - 0x7f & VDD\_1V8\_DIGI & float & 4 & r\\ - 0x83 & VDD\_1V8\_IOUT\_DIGI & float & 4 & r\\ + 0x53 & TEMP\_SENSOR & float & 4 & r\\ + 0x57 & EXT\_AIN & float & 4 & r\\ + 0x5b & MONITOR\_48V & float & 4 & r\\ + 0x5f & MONITOR\_48I & float & 4 & r\\ + 0x63 & MONITOR\_8VBUS & float & 4 & r\\ + 0x67 & MONITOR\_8IBUS & float & 4 & r\\ + 0x6b & MONITOR\_8V\_0 & float & 4 & r\\ + 0x6f & MONITOR\_8V\_1 & float & 4 & r\\ + 0x73 & MONITOR\_8V\_2 & float & 4 & r\\ + 0x77 & MONITOR\_8V\_3 & float & 4 & r\\ + 0x7b & VDD\_1V8\_ANA & float & 4 & r\\ + 0x7f & VDD\_1V8\_IOUT\_ANA & float & 4 & r\\ + 0x83 & VDD\_1V8\_DIGI & float & 4 & r\\ + 0x87 & VDD\_1V8\_IOUT\_DIGI & float & 4 & r\\ \hline - 0x87 & CommitHash & float & 4 & s\\ - 0x8b & CommitDirtyFlag & byte & 1 & s\\ - 0x8c & STM32UUID & 96bit & 12 & s\\ + 0x8b & CommitHash & float & 4 & s\\ + 0x8f & CommitDirtyFlag & byte & 1 & s\\ + 0x90 & STM32UUID & 96bit & 12 & s\\ \end{tabular} - \caption{memory mapping of the packed struct moved over i2c} + \caption{memory mapping of the packed struct moved over i2c, \mintinline{cpp}{addr} is the address to use, \mintinline{cpp}{type} is the c++ type, \mintinline{cpp}{size} is in bytes and \mintinline{cpp}{perm} denotes read-writability. writability} \label{registerbuffer} \end{figure} diff --git a/thesis.tex b/thesis.tex index 9fbb9a8..eafc9c2 100644 --- a/thesis.tex +++ b/thesis.tex @@ -20,7 +20,7 @@ \thispagestyle{empty} \begin{abstract} - Monitoring System status and regulation parameters within a complex System such as BrainScaleS, provides multiple critical points, which in case of misbehaviour can result in problems within the complete system. To reduce the eroneous data created within BarainScaleS, the PowerIt Board, one of its submodules, was upgraded and received a software ovehaul, containing calibration for the on board measurements and regultion capability for its most critical output terminal. + Monitoring System status and regulation parameters within a complex System such as BrainScaleS, provides multiple critical points, which in case of misbehaviour can result in problems within the complete system. To reduce the eroneous data created within BarainScaleS, the PowerIt Board, one of its submodules, was upgraded and received a software ovehaul, containing calibration for the on board measurements and regultion capability for its most critical output terminal. \end{abstract} \setcounter{tocdepth}{1} diff --git a/tikz/reticlepower.pdf b/tikz/reticlepower.pdf new file mode 100644 index 0000000000000000000000000000000000000000..7ed96164d549e5b0d1feda6b800d51f1211545d2 GIT binary patch literal 1227 zcmY!laBR8|4K6bU1BLvgEG`=xE`6WWy!4U`1tViK1qk5McgxHvNi9;) zcgsmENp(q0&QD3@va{nVE-6Y)%;l=M)f(j3ci4bq&vVfl1&$2|pRwAy*E;cQho1GS zzV&|n+bL=*!&aqqob5Sgz;{qwAV%%iho{pxC3w1-5{uezTm5xVj!D?CEN(5={tKt` zJw7_!Q9QKla#C-u^Mj4DOOj57)v(9gh@ElW!e*K-qPYFQ)eAN=S=M!3eH;J7YF0E~ zW&V^v+u(P-TzBS&8%G7|#%70=Of^%{E;`$~JK;*pg%!VcJaH9q_UimRafZa^X-m|T zjMhxu&bfFRt8k{V%Caz(dwtg@ug>kLSg>KE{rQajN6+}1E9bqw{or(9!adPxn}faA zyq{?Q*QCBqzMzOJH7^C~Z6FI2WQGPvVHZ%8pHi9(3@VL+l(dl42w)JK80Z;VYI5m2 z1H-B$A1DJ9hH*3V^IU)-s-WRwWn^GzVPI}#ZfI&?ZfdG+V5Dwfpbk{$o1a2RNk~y* zK|yK?FnSVmic`7t143LQ^xR5wa*`7B@<470$;d2L03wK+bQHo;i;96(D;Vn;ni!f| z8kw2u8tIwA+zNJ~f=^~ysshMS`i@1(89;7cX@#ajc0poEMsaGQLK)NuGd*KH15Hq3 zfCh&-QfP!!7NjcZ`zK`um*jHk`ze@%Qc_WIiGr~uBAFQxpUiyw&*mL65NLT{*Hy{X z!^zj#V)3EcVd|xbb7Fp-0scpOBY|~{~5m1 z@L)`?_OYqoW$(*(hqYiyT!t9I84;A4#-;C>my%kc5N)7fXcWt(ADmg03S@EVhbu%I zDi|pk0>y&z^Gg&gf!c#Ws?+inzzG$^aZ!l2F>rBmb2BxybaiodvUGEGF*7zXG%z+Y zH8(VJaxyYBwNoIh1ZWAgtS~W!78MGF%L?9OI|UgO1eiB&?N?u-Z?(Yb6bt(-!4GFj tLbe1bh<#FgZ@8rQ)h9-Wb4=SY!=tz)v8be?2p9sE#=x>m)z#mP3jkMIyX*h} literal 0 HcmV?d00001 diff --git a/tikz/reticlepower.svg b/tikz/reticlepower.svg new file mode 100644 index 0000000..4d4e3e0 --- /dev/null +++ b/tikz/reticlepower.svg @@ -0,0 +1,75 @@ + + + + diff --git a/tikz/reticlepower.synctex(busy) b/tikz/reticlepower.synctex(busy) new file mode 100644 index 0000000..e69de29 diff --git a/tikz/reticlepower.tex b/tikz/reticlepower.tex new file mode 100644 index 0000000..c631a54 --- /dev/null +++ b/tikz/reticlepower.tex @@ -0,0 +1,14 @@ +\documentclass[convert={outfile=\jobname.svg}]{standalone} +\input{./tikzpreamble} + +\begin{document} +\begin{circuitikz}[scale=2] + + \draw[color=black, thick] + (0,0) + to [R, l={R0}, short, o-] (0,1) + to [R, l={R1}, short, o-] (0,2) + ; + +\end{circuitikz} +\end{document}