update 20180814

data/theory/mktheory.py

@@ -1,11 +1,24 @@
 import matplotlib.pyplot as plt
 import numpy as np
+import wafer
 
 plt.style.use('bmh')
 plt.rcParams['axes.facecolor'] = 'white'
 plt.figure(figsize=(8, 3))
 
 
+def gen_reticle_empty():
+    plt.clf()
+
+    w = wafer.WaferRepr()
+    _, ax = plt.subplots()
+    w.placeim(ax, (0, 0))
+
+    ax.axis('off')
+    ax.set_aspect("equal")
+    plt.savefig('wafer.pdf')
+
+
 def gen_48v_theory():
     xdata = np.linspace(43, 53, 100)
     ydata = xdata / 241 * 8 * 1.1
@@ -53,3 +66,4 @@ if __name__ == "__main__":
     gen_48v_theory()
     gen_48i_theory()
     gen_1v8_theory()
+    gen_reticle_empty()

data/theory/wafer.py

@@ -0,0 +1 @@
+../../../pitstop/wafer.py

parts/theory.tex

@@ -113,16 +113,6 @@ This equation is in contrast to all previous behavior models not of a linear nat
 \subsection{1.8V Output Current}
 The circuit for measuring current is also quite straight forward. It consists of a current sensing IC, which is Hall sensor based, and is in series with the wafer connection. One each for digital and analog.
 
-
-\section{ADC Calibration}
-
-As mentioned beforehand, the actual hardware will differ in behavior from its theoretical counterpart. THese discrepancies will in fact differ by more than a safe to assume noise on our signal. Therefore we can say that all signals with a signoficant difference of behavior ($\approx 5\%$) will need to be corrected.
-
-To calibrate these readouts we need to employ some simple actions.
-
-\subsection{serial ADC readout}
-While the measurements done by the STM32-Chip are using a 12bit ADC, we don't have enough of these inside to be able to completely parallelize the measurements, also only one ADC will be connected to all connected Pins and switch between them.
-
 \begin{figure}[H]
     \centering
 
@@ -147,45 +137,59 @@ While the measurements done by the STM32-Chip are using a 12bit ADC, we don't ha
 
 \end{figure}
 
+\section{ADC Calibration}
+
+As mentioned beforehand, the actual hardware will differ in behavior from its theoretical counterpart. These discrepancies will in fact differ by more than we can accept and use without countermeasures. Therefore we can say that all signals with a signoficant difference of behavior ($\approx 5\%$) will need to be corrected.
+
+To calibrate these readouts we need to employ some simple actions.
+
+\subsection{serial ADC readout}
+While the measurements done by the STM32-Chip are using a 12bit ADC, there are not enough of these inside the chip to be able to completely parallelize the measurements, so only one ADC will be switching between all connected pins. This Behavior can be problematic in regards to measuring accurately. The timing used to measure a single line can be programmatically set from 3 up to 480 clock ticks\footnote{this clock is the internal adc clock, with a frequency of }
+
 \section{1.8V Output Regulation}
-%\section{Firmware Requirements}
+For Regulting the Output the method used is a numerical one, we calculate the voltage wanted at the putpu terminal and then we calculate a potentiometer setting, which changes the voltage produced (see \autoref{fig:gen18v}).
+The second part is already done beforehand and then available as lookup table to the firmware. On the other hand, to calculate the voltage to ouput, it is necessary to classify the connections between the PowerIts ouput terminals and the reticle.
 
-\section{Power Wafer}
-To test the 1.8V Regulation the so called Power Wafer is going to be used, it bahves similarly to a in BrainScales used ``fuctional'' Wafer module. But it is fundamentally different, as it cannot be used for computation, but only to test for voltages and currents. Its internals behave like switchable ohmic resistors, which provides us with a macimum power draw per section (Reticle) of what is allowed inside a usable wafer.
-
-Like its counterparts, it has the same Layout
+\subsection{Power Wafer}
+To test the 1.8V Regulation the so called Power Wafer is going to be used, it bahves similarly to a in BrainScales used ``fuctional'' Wafer module. But it is fundamentally different, as it cannot be used for computation, but only to test for voltages and currents. Its internals behave like switchable ohmic resistors, which provides us with a maximum powerdraw per Reticle of what is possible inside a usable wafer module.
 
 \begin{figure}[H]
     \centering
-    \includegraphics[width=\columnwidth]{./pitstop/20180727/ret_pic.pdf}
-    \caption{example diagram of power wafer, 16 Reticles in use}
+    \includegraphics[width=.8\columnwidth]{./data/theory/wafer.pdf}
+    \caption{reticle diagram of a wafer in BrainScaleS, orientation as used in software and to better visualize connections on the wafer. All 48 Reticles are shown, all numbered from top left to bottom right}%
+    \label{fig:wafer}
 \end{figure}
 
 \begin{figure}[H]
     \centering
-    \includegraphics[width=1\columnwidth]{./pics/waferpcb.png}
-    \caption{part of the mainpcb on which a wafer is placed, in its realworld orientation, visible are the 48 Reticles and two terminals each for 1.8V Digital and Analog}%
-    \label{}
+    \includegraphics[width=.7\columnwidth]{./pics/waferpcb.png}
+    \caption{part of the mainpcb on which a wafer is placed, in its realworld orientation (rotated 45° from \autoref{fig:wafer}), visible are the 48 Reticles and two terminals each for 1.8V Digital (blue) and Analog (red)}%
+    \label{fig:mainpcb}
 \end{figure}
 
-and each of the 48 Reticles can be accessed, digitaly as well as electricaly.
+It has the same layout as its system counterparts and each of the 48 Reticles can be accessed, digitaly as well as electricaly.
+Each Reticle is connected to its corresponding CURE Board, which can read voltages of each reticle, right after the PowerFETs, reponsible for switching on power to a Reticle (switches in \autoref{fig:retmodel})
 
-For this work the circuit model in \autoref{retmodel} can be used to describe the connections, powering these Reticles.
+Another specialization of the Power wafer is, that all reticles voltages are connected directly to pins on the Analog Readout Boards~\cite{anabpower}. There it is possible to measure a voltage, which is the one after the load resistors in \autoref{fig:retmodel}
+
+\subsection{Simple Wafer Resistance Model (SWRM)}
+
+The circuit in \autoref{fig:retmodel} can be used, as a first step, to describe the connections powering Reticles inside a wafer.
 
 \begin{figure}[H]
     \centering
     \includegraphics[width=.4\columnwidth]{./tikz/reticlepower.pdf}
-    \caption{model of the to measure resistances and their currents, $R_0$ describes the resistance of a connection between the PowerIt Output and up to the FET, while $R_1$ is a Resistance between FET and Reticles. The measurement is done between a Output Terminal on the PowerIt an a correspontingpin on a Ana-Board}%
-    \label{retmodel}
+    \caption{model of the to measure resistances and their currents, $R_0$ describes the resistance of a connection between the PowerIt Output and up to the FET, while $R_1$ is a Resistance between FET and Reticles. The measurement is done between Output Terminals on the PowerIt and pins on a Analog readout board}%
+    \label{fig:retmodel}
 \end{figure}
 
-This model allowes for two fixed resistance values and their respective currents. The current flowing through $R_1$ will be either 0 or a constant current $I_{ret}$. The current through $R_0$ will change depending on the number of reticles that are powered $n_{ret}$
+SWRM allowes for two fixed resistance values and their respective currents. The current flowing through $R_1$ will be either 0 or a constant current $I_{ret}$. The current through $R_0$ will change depending on the number of reticles that are powered $n_{ret}$
 
 \begin{align}
     I_{ges} = n_{ret} \cdot I_{ret}
 \end{align}
 
-Therefore the voltage Differential as measured by a Voltmeter (\autoref{retmodel}) can be described with \autoref{eq:vdip}
+Therefore the voltage Differential as measured by a Voltmeter (see \autoref{fig:retmodel}) can be described with \autoref{eq:vdip}
 
 \begin{align} \label{eq:vdip}
     V_{dip} =&\ V_{R_1} + V_{R_0} \nonumber\\
@@ -193,8 +197,7 @@ Therefore the voltage Differential as measured by a Voltmeter (\autoref{retmodel
             =&\ I_{ret} \cdot \left( R_1 + R_0 \cdot n_{ret} \right)
 \end{align}
 
-Combining Equations~\ref{eq:rset},~\ref{eq:vout} and  %TODO
-we gather \autoref{eq:fullreg}
+Combining Equations~\ref{eq:rpot},~\ref{eq:rset}, and~\ref{eq:vout}, we gather \autoref{eq:fullreg}. This equation is a reversed function of the one used in \autoref{fig:gen18v}
 
 \begin{align} \label{eq:fullreg}
     P_{val} = \frac{%
@@ -205,8 +208,7 @@ we gather \autoref{eq:fullreg}
     \frac{256}{10k\Omega}
 \end{align}
 
-inside the code used for Regulation %TODO: reference
-, \autoref{eq:fullreg} will be used to create a lookup table, while \autoref{eq:vout2} will be used at runtime, for which \autoref{eq:vdip} and~\ref{eq:voff} are needed.
+inside the code used for Regulation, \autoref{eq:fullreg} will be used to create a lookup table, while \autoref{eq:vout2} will be used at runtime, for which \autoref{eq:vdip} and~\ref{eq:voff} are needed.
 
 \begin{align} \label{eq:voff}
     V_{dip} =& V_O - V_{off}\\
@@ -214,7 +216,12 @@ inside the code used for Regulation %TODO: reference
 \end{align}
 
 
-Alternatively:
+\subsection{Distance Wafer Resistance Model}
+
+Although the through SWRM gained functions are useful for determinig a theoretical Regulation procedure, it is still not near the realworld scenario.
+In a wafer, the distance between reticles and voltage connector (see \autoref{fig:mainpcb}) are resulting in additional resistance, proportionally.
+
+Therefore we adapt the DWRM after Circuit~\ref{fig:retmodelshell} in which each different Distance requires additional Resistors.
 
 \begin{figure}[H]
     \centering
@@ -223,11 +230,11 @@ Alternatively:
     \label{fig:retmodelshell}
 \end{figure}
 
-so we expect the voltage to change depending on the reticles distance to the nearest voltage supply pad.
+With this model the voltage is now expected to change depending on the reticles distance instead of being the same. The distances inside a wafer are visualized in \autoref{fig:retmodelrdist}
 
 \begin{figure}[H]
     \centering
     \includegraphics[width=\columnwidth]{../pitstop/20180809/reticel_rtheo.pdf}
-    \caption{theoretr}%
+    \caption{Distances of reticles to the nearest voltage suppling connection for DWRM, distance is in reticle-side length}%
     \label{fig:retmodelrdist}
 \end{figure}

thesis.tex

@@ -24,7 +24,8 @@
     \thispagestyle{empty}
 
     \begin{abstract}
-        Monitoring System status and regulation parameters within a complex System such as BrainScaleS, provides multiple critical points, which in case of misbehaviour can result in problems within the complete system. To reduce the eroneous data created within BarainScaleS, the PowerIt Board, one of its submodules, was upgraded and received a software ovehaul, containing calibration for the on board measurements and regultion capability for its most critical output terminal. 
+        Monitoring System status and regulation parameters within a complex System such as BrainScaleS, provides multiple critical points, which in case of misbehaviour can result in problems within the complete system.
+        To reduce the eroneous data created within BarainScaleS, the PowerIt Board, one of its submodules, was upgraded and received a software ovehaul, containing calibration for the on board measurements and regultion capability for its most critical output terminal. 
         \\\\
 
         Monitoring System Status und Regulations Parameter innherhalb eines komplexen Systems, wie etwa BrainScaleS, entahlten kritische Punkte des Systems, welche im Flalle eines Fehlers in Promblemen mit dem kompletten System resultieren können. Um die innerhalb von BrainScales erzeugten fehlerhaften Daten zu reduzieren, hat das PowerIt Submodul ein Firmware Upgrade erhalten, diese enthält nun Kalibrationen für die Board eigenen Messungen, sowie die Fähigkeit die Systemkritischen Ausgänge zu regulieren.