update regulation and correct some things

data/m03_poticalib/processing_poticalib.py

@@ -9,7 +9,8 @@ lognum = 2
 plt.ioff()
 plt.style.use('bmh')
 plt.rcParams['axes.facecolor'] = 'white'
-plt.figure(figsize=(8,6))
+fig, axa = plt.subplots(1, figsize=(8,4), sharex='all', gridspec_kw={'height_ratios': [1]})
+axa = [axa]
 data = pd.read_csv("./log_poticalib_ana_{:02d}.csv".format(lognum))
 
 print(data)
@@ -33,29 +34,29 @@ data['r_bcu/kohm'] = 2*4.7+1/(1/data['r_restheo/kohm']+1/75)
 
 data['v_bcutheo/v'] = 0.7+0.7*30.1/(data['r_bcu/kohm']+6.49)
 
-plt.errorbar(
+axa[0].errorbar(
     data['r_bcu/kohm'],
     data['v_keith/v'],
     yerr=data['dv_keith/v'],
-    label="V$_{Keith,IV8A}$",
+    label="V$_{Keith,1.8V,ana}$",
     fmt='.'
 )
-plt.errorbar(
+axa[0].errorbar(
     data['r_bcu/kohm'],
     data['v_pit/v'],
     yerr=data['dv_pit/v)'],
-    label="V$_{PIT,IV8A}$",
+    label="V$_{PIT,1.8V,ana}$",
     fmt='.'
 )
-plt.plot(
+axa[0].plot(
     data['r_bcu/kohm'],
     data['v_bcutheo/v'],
     label="V$_{BCU,O}$"
 )
 
-plt.xlabel('$R_{BCU,Set}$/k$\Omega$')
+axa[0].set_xlabel('$R_{BCU,Set}$/k$\Omega$')
-plt.ylabel('V$_{1V8A}$/V')
+#axa[1].set_ylabel('Residuals / %$_{err}$')
-plt.legend()
+axa[0].set_ylabel('V$_{1.8V, Analog}$/V')
-#-plt.savefig("2kw_direct.png")
+axa[0].legend()
 
 plt.savefig("adccalib_{:02d}.pdf".format(lognum), transparent=True)

data/m04_cycledepends/processing_cycledepends.py

@@ -21,7 +21,7 @@ plt.rcParams['axes.facecolor'] = 'white'
 fig, axarr = plt.subplots(
     2,
     1,
-    figsize=(10, 8),
+    figsize=(8, 6),
     gridspec_kw={'height_ratios':[4, 1]},
     sharex="col"
 )

data/m04_cycledepends/processing_cycledepends_raw.py

@@ -21,7 +21,7 @@ plt.rcParams['axes.facecolor'] = 'white'
 fig, axarr = plt.subplots(
     2,
     1,
-    figsize=(8, 6),
+    figsize=(8, 8),
     gridspec_kw={'height_ratios':[4, .8]}
 )
 plt.subplots_adjust(hspace=.5)

parts/experiments.tex

@@ -1,31 +1,31 @@
 %! TEX root = ../thesis.tex
 \chapter{Experiments}
-Now that the theoretical model sicomplete, experiments can be done to start checking that model and get results to use for in system components.
+Now that the theoretical model is complete, experiments can be done to start checking that model and get results to use for in system components.
 
 \section{Characterization}
 
-The first experiments to run are the caracterization of hardware behavior. These will then result in a PowerIt Calibration, which later then can be used as basis for creating a regulation method.
+The first experiments to run are the characterization of hardware behavior. These will then result in a PowerIt Calibration, which later then can be used as basis for creating a regulation method.
 
 \subsection{sampling time}
     First up was selecting an optimal number of cycles for which the adc will probe a to it connected pin, like described in \autoref{sec:adc}.
 
     In this case the uncalibrated measurement of input voltage was taken as example, and repeated with each of the possible 8 settings.
 
-    To be able to compare a reference voltage measurement was taken with an external Voltmeter.
+    To be able to compare a reference voltage measurement was taken with an external Voltmeter\footnote{Keithley K2100}.
     The resulting errors, from a set Voltage, can be seen in figures \ref{sampleticks1}
 
     \begin{figure}
         \centering
         \hspace*{-.175\columnwidth}
         \includegraphics[width=1.3\columnwidth]{./data/m04_cycledepends/cycledepends_20180529.pdf}
-        \caption{plotted difference from set input voltage, and fitted linearly, May 29th 2018, $\approx$32\si\degree C}
+        \caption{up: input difference from set voltage vs set voltage for different possible scaler values; down: gain error of the linear fitted curves vs set scaler value (May 29th 2018, $\approx$32\si\degree C)}%
         \label{sampleticks1}
     \end{figure}
 
-    \autoref{sampleticks1} contains the relative error of the measured voltage compared to the theoretical, set input voltages. therefore the reference measurements (yellow), taken with an external multimeter, are not at 0.
+    \autoref{sampleticks1} contains the absolute error of the measured voltage compared to the theoretical, set input voltages. therefore the reference measurements (yellow), taken with an external Voltmeter, are not at 0.
-    Also shown are the calculated gain erors, in case of all 8 settings.
+    Also shown are the calculated gain errors, in case of all 8 settings.
 
-    Important to note is the relative error in only the 0th case, here the \verb|cycleTime|-Setting was set to 0 and therefore the smallest available sampletime of 3 Ticks. This excludes 0 a possible value to use. All other measurements are within errormargin of each other, and because a smaller timeframe is preferred, the best value to use is 1, resulting in a measuretime of 15 Ticks. 
+    Important to note is the relative error in only the 0th case, here the \verb|cycleTime|-Setting was set to 0 and therefore the smallest available sampling time of 3 Ticks. This excludes 0 a possible value to use. All other measurements are within error margin of each other, and because a smaller time frame is preferred, the best value to use is 1, resulting in a measure time of 15 Ticks. 
 
     % TODO: move to appendix
     %\begin{figure}[H]
@@ -38,8 +38,8 @@ The first experiments to run are the caracterization of hardware behavior. These
 
 \subsection{Voltages}
 
-    Now that a sampleTime is chosen, it is possible to proceed with the voltage calibration measureemnts.
+    Now that a sample time is chosen, it is possible to proceed with the voltage calibration measurements.
-    Note, that Measuremts are expected to be less accurate, the more components are contained in their respective measurement circuit. Because small errors will accumulate and in e.g. the case of 48V's be amplified by a factor of 8.
+    Note, that measurements are expected to be less accurate, the more components are contained in their respective measurement circuit. Because small errors will accumulate and in e.g. the case of 48V's be amplified by a factor of 8.
 
     \subsubsection{48V Input}
 
@@ -47,13 +47,13 @@ The first experiments to run are the caracterization of hardware behavior. These
             \centering
             \vspace{-1cm}
             \hspace*{-.16\columnwidth}
-            \includegraphics[width=1.3\columnwidth]{../pitstop/20180815/calib_v48.pdf}
+            \includegraphics[width=1.3\columnwidth]{../pitstop/20180821/calib_v48.pdf}
             \caption{Calibration of input voltage, plotted are a external measurement and internal values, vs the recalculated pin voltage based on the internal value and used default function (default coefficients see \autoref{pitdb-example})}%
             \label{v48_precalib}
         \end{figure}
 
         When looking at calibrating the input voltage (\autoref{v48_precalib}), we can clearly see a relatively constant offset of $\approx$1V.
-        In \autoref{v48_precalib} a polynomial fit of 2nd degree\footnote{A Fit of second degree will be used in the complete calibration process} is done and its coeffficients extracted (\autoref{pitdb}, line 9).
+        In \autoref{v48_precalib} a polynomial fit of 2nd degree\footnote{A Fit of second degree will be used in the complete calibration process} is done and its coefficients extracted (\autoref{pitdb}, line 9).
         These coefficients not only show an offset, but also some deviation in the incline and curve from the default values.
 
         \subsubsection{9.6V Output}
@@ -62,7 +62,7 @@ The first experiments to run are the caracterization of hardware behavior. These
             \centering
             \vspace{-1cm}
             \hspace*{-.16\columnwidth}
-            \includegraphics[width=1.3\columnwidth]{../pitstop/20180815/calib_v10.pdf}
+            \includegraphics[width=1.3\columnwidth]{../pitstop/20180821/calib_v10.pdf}
             \caption{Calibration of 9.6V output Voltage, plotted are an external measurement and internal values vs the recalculated pin voltage based on the default coefficients (\autoref{pitdb-example})}%
             \label{v10_precalib}
         \end{figure}
@@ -100,8 +100,8 @@ Note that the 9.6V Output does in fact not have a include circuit for measuring
             \hspace*{-.16\columnwidth}
             %TODO: transparent
             %\vspace{-1cm}
-            \includegraphics[width=1.3\columnwidth]{./pitstop/20180809/calib_i48.pdf}
+            \includegraphics[width=1.3\columnwidth]{../pitstop/20180821/calib_i48.pdf}
-            \caption{Calibration of input current adcs 21.06.2018}
+            \caption{Calibration of input current ADCs 21.06.2018}
             \label{}
         \end{figure}
 
@@ -111,7 +111,7 @@ Note that the 9.6V Output does in fact not have a include circuit for measuring
             \hspace*{-.15\columnwidth}
             %TODO: transparent
             %\vspace{-1cm}
-            \includegraphics[width=1.3\columnwidth]{./pitstop/20180809/calib_i18.pdf}
+            \includegraphics[width=1.3\columnwidth]{../pitstop/20180821/calib_i18.pdf}
             \caption{Pre Calibration Measurement of Output Current at the 1.8V Analog and Digital Terminal (2.7.2018)}
             \label{precalib18iana}
         \end{figure}
@@ -141,7 +141,7 @@ Note that the 9.6V Output does in fact not have a include circuit for measuring
 
 \section{1.8V Regulation}
 
-As Described beforehand the Output Voltages for both analog and digital can be adjusted to some degree and therefore we can compensate for the dropoff occuring between PowerIt Output Terminals and Reticles.
+As Described beforehand the Output Voltages for both analog and digital can be adjusted to some degree and therefore we can compensate for the dropoff occurring between PowerIt Output Terminals and Reticles.
 
 \begin{figure}[H]
     \centering
@@ -152,12 +152,12 @@ As Described beforehand the Output Voltages for both analog and digital can be a
 
 \subsection{Characterization of Dropoff}
 
-Wanting to observe and characterize the voltage drop, first the connections between PowerIt and Reticles can be measured with the in \autoref{fig:retmodel} described connections, which in actuallity are the PowerIT Terminal and corresponding analog readout pin on a Analog readout board.
+Wanting to observe and characterize the voltage drop, first the connections between PowerIt and Reticles can be measured with the in \autoref{fig:retmodel} described connections, which in actuality are the PowerIT Terminal and corresponding analog readout pin on a Analog readout board.
 
-To use the PowerWfer for testing one of the patterns in \autoref{fig:wpattern} will be used, each pattern has a aproximate currentdraw of 120A and will distribute heat and draw per terminal evenly.
+To use the PowerWafer for testing one of the patterns in \autoref{fig:wpattern} will be used, each pattern has a approximate current draw of 120A and will distribute heat and draw per terminal evenly.
 
 In \autoref{1v8dip} a single reticles (40) Voltage Dip for different Current Draws is visualized.
-A relatively linear trend and residuals of a trigonometric behavior can be observed (most likely the result of the inaccurately measureable current draw, which here is done inside the PowerIt).
+A relatively linear trend and residuals of a trigonometric behavior can be observed (most likely the result of the inaccurately measurable current draw, which here is done inside the PowerIt).
 
 \begin{figure}[H]
     \centering
@@ -177,15 +177,15 @@ The initial idea, to approach the correction of this dropoff is a Numerical: the
 
 To apply this approach, two assumptions need to be made:
 \begin{itemize}
-    \item all reticles have the same current draw (already nmot accurate, see \autoref{1v8dip})
+    \item all reticles have the same current draw (already not accurate, see \autoref{1v8dip})
-    \item all reticles experience the same Voltage Dip (as observed for Reticle 40)
+    \item all reticles experience the same Voltage Dip (as observed for reticle 40)
 \end{itemize}
 
 and the following four values are required, before a regulation can be attempted:
 \begin{itemize}
     \item \(I_{ret}\), the current draw of a single reticle,
-    \item \(R_0\), the Resistance between PowerIt and FET,
+    \item \(R_0\), the resistance between PowerIt and FET,
-    \item \(R_1\), the Resstance of a single Reticle
+    \item \(R_1\), the resistance of a single Reticle
 
     \item \(V_{off}\), the wanted Voltage at a Reticle
 \end{itemize}
@@ -253,12 +253,12 @@ So applying these Values, the following behavior for regulation can be visualize
     \label{fig:regswrm}
 \end{figure}
 
-The in \autoref{fig:regswrm} visualized values show the theoretical \(P_{val}\) for the corresponding Current, whlie all dotted parts depict the values wich would be needed to achieve full correction at the Reticle level. 
+The in \autoref{fig:regswrm} visualized values show the theoretical \(P_{val}\) for the corresponding Current, while all dotted parts depict the values which would be needed to achieve full correction at the Reticle level. 
 Note that the 1.8V regulation, should fail at about 80A of current draw.
 
-Now that the SWRM is appliable, what about the DWRM, which removes the assuption of a equal Voltage Dip per Reticle, applying an offset to the initially observed Voltage of each Reticle.
+Now that the SWRM is applicable, what about the DWRM, which removes the assumption of a equal Voltage Dip per Reticle, applying an offset to the initially observed Voltage of each Reticle.
 
-To account for that, the Voltage Dip per Reticle, in a simgle Reticle power state, was observed:
+To account for that, the Voltage Dip per Reticle, in a single Reticle power state, was observed:
 
 \begin{figure}[H]
     \centering
@@ -285,7 +285,7 @@ can be observed.
 \end{figure}
 
 \autoref{fig:wrdist} shows how those Voltages are Distributed over the complete PowerWafer.
-All white Reticles are not measurable, and those colored in Red and Yellow are the outliers in \autoref{fig:vdiphist}. Note that in a deployed, working, Wafer System inside BrainScaleS the iddle two Reticles are not used and also gicve grounds to ignoring the outliers.
+All white Reticles are not measurable, and those colored in Red and Yellow are the outliers in \autoref{fig:vdiphist}. Note that in a deployed, working, Wafer System inside BrainScaleS the middle two Reticles (19 \& 28) are not used and also give grounds to ignoring the outliers.
 
 This results in a distribution, which when combined with the spread of \(R_0\) from \autoref{fig:ret5corr}, gives an approximate range for all Reticles Voltage Dip at a given Current Draw (\autoref{fig:vrange}).
 
@@ -293,7 +293,7 @@ This results in a distribution, which when combined with the spread of \(R_0\) f
     \centering
     \hspace*{-.15\columnwidth}
     \includegraphics[width=1.3\columnwidth]{../pitstop/20180820/reticle_variance.pdf}
-    \caption{Expermentally obtained Voltage Ranges in which most Reticles Voltage Dip will lie, this does not include outliers}%
+    \caption{Experimentally obtained Voltage Ranges in which most Reticles Voltage Dip will lie, this does not include outliers}%
     \label{fig:vrange}
 \end{figure}
 

parts/theory.tex

@@ -7,7 +7,7 @@ Before discussing the experimental results it needs to be clear what circuitry i
 Keeping in mind, that these are theoretical values and will most likely not be exactly the same as those found in actual hardware, as all values given will always be within some error as defined by their manufacturer.
 
 Each of the three voltage regimes that will be observed on the PowerIt Board, 48V 9.6V and 1.8V, has a voltage- and in the cases of 48V and 1.8V also a current-measurement circuit. Additionally we have a temperature sensor built into the STM32 Chip.
-\subsection{48V Input Voltage}
+\subsection{48V Input Voltage}\label{sec:mon48v}
 \begin{figure}[H]
     \centering
     \includegraphics[width=.9\textwidth]{./tikz/mon48v.pdf}
@@ -47,20 +47,28 @@ This circuit results in the following equation for calculating the input voltage
     \label{mon48i}
 \end{figure}
 
-In case of the current measurement circuit we require the following:
+%In case of the current measurement circuit we require the following:
+THe circuit has to satisfy the following constraints:
 \begin{enumerate}
     \item use a shunt resistor, with minimal heat dissipation 
-    \item still providing a good resolution also within the Chips Specifications
+    \item still providing a good resolution also within the STM32-Chips Specifications
-\end{enumerate}
+\end{enumerate}~\\\\
+To accomplish that, the circuit is measuring the voltage over a small (\(\SI{500}{\micro\ohm}\)) shunt Resistor, while a current is flowing, resulting in a proportionality, by Ohms Law. The obtained Voltage is then decoupled and amplified by a factor of 8, as well as converted from a difference to single ended Voltage, with a amplification factor of 1.1.
 
-Here we use the same Amplifiers and so we can use the following equation for our input current:
+Here we use the same Amplifiers as in \autoref{sec:mon48v} and so we can use the following equation for our input current:
 \begin{align}
     I_\text{48V IN}\cdot R_\text{shunt} \cdot r_\text{diffOpAmp} \cdot r_\text{OpAmp} = V_\text{48I pin}\nonumber\\
     \Leftrightarrow\quad \frac{V_\text{48I pin}}{R_\text{shunt}} \cdot \frac{1}{r_\text{diffOpAmp}\cdot r_\text{OpAmp}} = I_\text{48V IN}
 \end{align}
 
+And applying the extrema of 0A and 41.7A, a voltage range from 0V to:
+\begin{align}
+    \SI{41.7}{\ampere}\cdot \SI{500}{\micro\ohm} \cdot 8\cdot 1.1 =& \SI{0.1833}{\volt}
+\end{align} 
+can be observed.
+
 \subsection{9.6V Output Voltage}
-This Circuit consists of a a simple 1:4 Voltage Divider.
+This Circuit consists of a a simple 1:3 Voltage Divider.
 
 \begin{figure}[H]
     \centering
@@ -82,7 +90,7 @@ This Circuit consists of a a simple 1:4 Voltage Divider.
 
 \end{figure}
 
-And the following equation shows that:
+And the following equation can be used to calculate that voltage:
 \begin{align}
     V_\text{10V PIN} = \frac{V_\text{10V IN} \cdot R_1}{R_1 + R_2}
 \end{align}
@@ -90,24 +98,31 @@ And the following equation shows that:
 
 \subsection{1.8V Output Voltage}
 
-until now the voltages and current could only be measured, now the mechanism for setting a resulting Voltage at the 1.8V Terminals is known. \autoref{fig:gen18v} is the circuit for generating 1.8V, it consists of a power module and a resulting resistance at given pind, defined by R$_\text{series}$, R$_\text{parallel}$ and R$_{pot}$, whose job is to set the output to a given voltage of around 1.8V, but we can vary R$_\text{pot}$, because this resistance is set vie a digital potentiometer.
+To measure this Voltage the output is directly connected to a pin on the STM32-Chip.
+
+Until now the voltages and current could only be measured, now the mechanism for setting a resulting Voltage at the 1.8V Terminals is known.
+\autoref{fig:gen18v} is the circuit for generating 1.8V. 
+It consists of a power module and a resulting resistance between two pins, defined by R$_\text{series}$, R$_\text{parallel}$ and R$_{pot}$.
+The Resistances job is to set the output to a given voltage of around 1.8V, but we can vary R$_\text{pot}$, because this resistance is set vie a digital potentiometer.
 \begin{figure}[t]
     \centering
     \includegraphics[width=.55\textwidth]{./tikz/gen18v.pdf}
-    \caption{Circuit for generating a changable Output Voltage, consisting of the DC-DC Converter, a resistor chain, supply voltage (left) and resulting voltage (right)}%
+    \caption{1.8V supply circuit, featuring a DC-DC Converter, a resistor chain, supply voltage (left) and resulting voltage (right)}%
     \label{fig:gen18v}
 \end{figure}
 
-The in \autoref{fig:gen18v} used 1.8V Converters have a characteristic formual~\cite{pth08t}, and the in this circuit used Potentiometer  is a linear 10k$\Omega$ Rheostat resulting in the following equations:
+The in \autoref{fig:gen18v} used 1.8V Converters have a characteristic formula~\cite{pth08t}, and the in this circuit used Potentiometer  is a linear 10k$\Omega$ Rheostat resulting in the following equations:
 
 \begin{align}
     R_{potentiometer} =& P_{val} \frac{10k\Omega}{256} \label{eq:rpot}\\
     R_{SET} =& 1 / \left(\frac{1}{R_{potentiometer}} + \frac{1}{R_{parallel}}\right) + R_{series}\nonumber\\
     =& \frac{R_\text{potentiometer}\cdot R_\text{parallel}}{R_\text{potentiometer} + R_\text{parallel}} + R_\text{series}\label{eq:rset}\\
-    V_O =& \frac{30.1 k\Omega}{R_{SET} + 6.49 k\Omega} \cdot 0.7V + 0.7V\label{eq:vout}
+    V_\text{MONITOR\_1V8} =& \frac{30.1 k\Omega}{R_{SET} + 6.49 k\Omega} \cdot 0.7V + 0.7V\label{eq:vout}
 \end{align}
 
-This equation is in contrast to all previous behavior models not of a linear nature but proportional to $\frac1x$ as visualized in \autoref{fig:beh1v8}
+%This equation is in contrast to all previous behavior models not of a linear nature but proportional to $\frac1x$ as visualized in \autoref{fig:beh1v8}
+\autoref{eq:vout} is visualized in \autoref{fig:gen18v}.
+Note that this Equation is proportional to \(\frac 1x\)
 
 \begin{figure}[H]
     \centering
@@ -117,11 +132,10 @@ This equation is in contrast to all previous behavior models not of a linear nat
     \label{fig:beh1v8}
 \end{figure}
 \subsection{1.8V Output Current}
-The circuit for measuring current is also quite straight forward. It consists of a current sensing IC, which is Hall sensor based, and is in series with the wafer connection. One each for digital and analog.
+The circuit for measuring the outgoing current over 1.8V, consists of a current sensing IC, which is Hall sensor based. Each connection (digital and analog) has this ic in series to its load.
 
 \begin{figure}[H]
     \centering
-
     \resizebox{.55\columnwidth}{.12\paperheight}{%
         \begin{circuitikz}[scale=2]
             \draw[color=black, thick]
@@ -140,43 +154,61 @@ The circuit for measuring current is also quite straight forward. It consists of
             to [short, *-] (3, 1) node[right, draw=black] {VDD\_1V8\_*};
         \end{circuitikz}
     }
-
+    \caption{1.8V current sensing circuit, featuring a acs758, hall sensor based current sensing IC, input voltage (left) and output voltage (right)}%
-\end{figure}
+    \label{fig:mon18i}
+\end{figure}~\\
+The IC is rated for a maximum constant current draw of 100A, and has the following behavior:
+\begin{align}
+    I_\text{1.8V, in} \cdot \SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~V_\text{MONITOR\_1I8\_*}
+    \intertext{which gives for the extremes:}
+    \SI 0\ampere \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{0.12}{\volt}\\
+    \SI{100}{\ampere} \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{0.52}{\volt}
+\end{align}
 
 \section{ADC Calibration}
 
-As mentioned beforehand, the actual hardware will differ in behavior from its theoretical counterpart. These discrepancies will in fact differ by more than we can accept and use without countermeasures. Therefore we can say that all signals with a signoficant difference of behavior ($\approx 5\%$) will need to be corrected.
+As mentioned beforehand, the actual hardware will differ in behavior from its theoretical counterpart.
+Therefore it is possible to say that all signals with a significant difference of behavior ($\approx 5\%$) will need to be corrected.
 
 To calibrate these readouts we need to employ some simple actions.
 
 \subsection{serial ADC readout}\label{sec:adc}
-While the measurements done by the STM32-Chip are using a 12bit ADC, there are not enough of these inside the chip to be able to completely parallelize the measurements, so only one ADC will be switching between all connected pins. This Behavior can be problematic in regards to measuring accurately. The timing used to measure a single line can be programmatically set from 3 up to 480 clock ticks\footnote{this clock is the internal adc clock, with a frequency of }
+The measurements will be done by the STM32-Chip, which uses 12bit ADCs.
+A single ADC will be switching between all connected pins. 
+This Behavior can be problematic in regards to measuring accurately.
+The timing used to measure a single pin can be programmatically set from 3 up to 480 clock ticks\footnote{this clock is the internal adc clock, with a frequency of \SI{159}{\hertz}}
 
 \section{1.8V Output Regulation}
-For Regulting the Output the method used is a numerical one, we calculate the voltage wanted at the putpu terminal and then we calculate a potentiometer setting, which changes the voltage produced (see \autoref{fig:gen18v}).
+For regulating the Output the method used is a relatively simple one.
-The second part is already done beforehand and then available as lookup table to the firmware. On the other hand, to calculate the voltage to ouput, it is necessary to classify the connections between the PowerIts ouput terminals and the reticle.
+The voltage, wanted at the output terminal, will be calculated and then a corresponding potentiometer setting can be extracted, which changes the voltage produced (see \autoref{fig:gen18v}).
+The second part is already done beforehand and then available as a lookup table\footnote{mV-Scale, from 1.549V to 2.022V} to the firmware.
+On the other hand, to calculate the voltage to output, it is necessary to classify the connections between the PowerIts output terminals and the reticle.
 
 \subsection{Power Wafer}
-To test the 1.8V Regulation the so called Power Wafer is going to be used, it bahves similarly to a in BrainScales used ``fuctional'' Wafer module. But it is fundamentally different, as it cannot be used for computation, but only to test for voltages and currents. Its internals behave like switchable ohmic resistors, which provides us with a maximum powerdraw per Reticle of what is possible inside a usable wafer module.
+To test the 1.8V Regulation the so called Power Wafer is going to be used, it can be controlled similar to a in BrainScales used, functional, Wafer module.
+But it is fundamentally different, as it cannot be used for computation, but only to test for voltages and currents.
+Its internals behave like ohmic resistors, which provides us with a maximum power draw per Reticle of what is possible inside a usable wafer module.
 
 \begin{figure}[H]
     \centering
     \includegraphics[width=.8\columnwidth]{./data/theory/wafer.pdf}
-    \caption{reticle diagram of a wafer in BrainScaleS, orientation as used in software and to better visualize connections on the wafer. All 48 Reticles are shown, all numbered from top left to bottom right}%
+    \caption{reticle diagram of a wafer in BrainScaleS. All 48 Reticles are shown}%
     \label{fig:wafer}
 \end{figure}
 
 \begin{figure}[H]
     \centering
     \includegraphics[width=.7\columnwidth]{./pics/waferpcb.png}
-    \caption{part of the mainpcb on which a wafer is placed, in its realworld orientation (rotated 45° from \autoref{fig:wafer}), visible are the 48 Reticles and two terminals each for 1.8V Digital (blue) and Analog (red)}%
+    \caption{part of the mainpcb on which a wafer is placed, visible are the 48 Reticles and two terminals each for 1.8V Digital (blue) and Analog (red), which correspond to the output terminals on a PowerIt}%
     \label{fig:mainpcb}
 \end{figure}
 
 It has the same layout as its system counterparts and each of the 48 Reticles can be accessed, digitaly as well as electricaly.
-Each Reticle is connected to its corresponding CURE Board, which can read voltages of each reticle, right after the PowerFETs, reponsible for switching on power to a Reticle (switches in \autoref{fig:retmodel})
+Each Reticle is connected to its corresponding CURE Board.
+Those can read voltages of each reticle, but not at the same position as an AnaB.
+They read right before \(R_1\) in \autoref{fig:retmodel}.
 
-Another specialization of the Power wafer is, that all reticles voltages are connected directly to pins on the Analog Readout Boards~\cite{anabpower}. There it is possible to measure a voltage, which is the one after the load resistors in \autoref{fig:retmodel}
+Another specialization of the Power wafer is, that all reticles analog and digital 1.8V lines are connected directly to pins on the Analog Readout Boards~\cite{anabpower}. There it is possible to measure a voltage, which is the one after the load resistors in \autoref{fig:retmodel}
 
 \subsection{Simple Wafer Resistance Model (SWRM)}\label{sec:swrm}
 
@@ -185,7 +217,7 @@ The circuit in \autoref{fig:retmodel} can be used, as a first step, to describe
 \begin{figure}[H]
     \centering
     \includegraphics[width=.4\columnwidth]{./tikz/reticlepower.pdf}
-    \caption{model of the to measure resistances and their currents, $R_0$ describes the resistance of a connection between the PowerIt Output and up to the FET, while $R_1$ is a Resistance between FET and Reticles. The measurement is done between Output Terminals on the PowerIt and pins on a Analog readout board}%
+    \caption{model of the to measure resistances and their currents, $R_0$ describes the resistance of a connection between the PowerIt Output and up to the FET (depicted as switch), while $R_1$ is a Resistance between FET and Reticles. The measurement is done between Output Terminals on the PowerIt and pins on a Analog readout board}%
     \label{fig:retmodel}
 \end{figure}
 
@@ -195,21 +227,21 @@ SWRM allowes for two fixed resistance values and their respective currents. The
     I_{ges} = n_{ret} \cdot I_{ret}
 \end{align}
 
-Therefore the voltage Differential as measured by a Voltmeter (see \autoref{fig:retmodel}) can be described with \autoref{eq:vdip}
+Therefore the voltage dip \(V_\text{dip}\) as measured by a Voltmeter (see \autoref{fig:retmodel}) can be described with \autoref{eq:vdip}
 
 \begin{align} \label{eq:vdip}
-    V_{dip} =&\ V_{R_1} + V_{R_0} \nonumber\\
+    V_\text{dip} =&\ V_{R_1} + V_{R_0} \nonumber\\
-            =&\ R_1 \cdot I_{ret} + R_0 \cdot I_{ges} \nonumber\\
+            =&\ R_1 \cdot I_\text{ret} + R_0 \cdot I_\text{ges} \nonumber\\
-            =&\ I_{ret} \cdot \left( R_1 + R_0 \cdot n_{ret} \right)
+            =&\ I_\text{ret} \cdot \left( R_1 + R_0 \cdot n_\text{ret} \right)
 \end{align}
 
-Combining Equations~\ref{eq:rpot},~\ref{eq:rset}, and~\ref{eq:vout}, we gather \autoref{eq:fullreg}. This equation is a reversed function of the one used in \autoref{fig:gen18v}
+Combining Equations~\ref{eq:rpot},~\ref{eq:rset}, and~\ref{eq:vout}, we gather \autoref{eq:fullreg}. This equation is a reversed function of the one given by the 1.8V supplying IC (see \autoref{fig:gen18v})
 
 \begin{align} \label{eq:fullreg}
-    P_{val} = \frac{%
+    P_\text{val} = \frac{%
-        R_{par} \left[ \left( \frac{0.7V \cdot 30.1k\Omega}{V_{O}-0.7V} - 6.49k\Omega \right) - R_{ser}\right]
+        R_\text{par} \left[ \left( \frac{0.7V \cdot 30.1k\Omega}{V_{O}-0.7V} - 6.49k\Omega \right) - R_\text{ser}\right]
     }{%
-        R_{par} + \left( \frac{0.7V \cdot 30.1k\Omega}{V_{O}-0.7V} - 6.49k\Omega \right) - R_{ser}
+        R_\text{par} + \left( \frac{0.7V \cdot 30.1k\Omega}{V_{O}-0.7V} - 6.49k\Omega \right) - R_\text{ser}
     }\cdot
     \frac{256}{10k\Omega}
 \end{align}
@@ -217,8 +249,8 @@ Combining Equations~\ref{eq:rpot},~\ref{eq:rset}, and~\ref{eq:vout}, we gather \
 inside the code used for Regulation, \autoref{eq:fullreg} will be used to create a lookup table, while \autoref{eq:vout2} will be used at runtime, for which \autoref{eq:vdip} and~\ref{eq:voff} are needed.
 
 \begin{align} \label{eq:voff}
-    V_{dip} =& V_O - V_{off}\\
+    V_\text{dip} =& V_O - V_\text{off}\\
-    \Rightarrow V_O =& I_{ret} \cdot \left( R_1 + R_0 \cdot n_{ret} \right) + V{off}\label{eq:vout2}
+    \Rightarrow V_O =& I_\text{ret} \cdot \left( R_1 + R_0 \cdot n_\text{ret} \right) + V_\text{off}\label{eq:vout2}
 \end{align}
 
 \subsection{Distance Wafer Resistance Model}
@@ -239,7 +271,8 @@ With this model the voltage is now expected to change depending on the reticles
 
 \begin{figure}[H]
     \centering
-    \includegraphics[width=\columnwidth]{../pitstop/20180815/reticel_rtheo.pdf}
+    \hspace*{-.14\columnwidth}
+    \includegraphics[width=1.2\columnwidth]{../pitstop/20180821/reticel_rtheo.pdf}
     \caption{Distances of reticles to the nearest voltage supplying connection for DWRM, distance is in reticle-side length}%
     \label{fig:retmodelrdist}
 \end{figure}

tikz/mon48i.tex

@@ -30,8 +30,9 @@
         to (2.46,3)
         to [short,-o](6,3) node[right] {$V_{SS} = 3.3V$}
     (fdoa.up)+(-.2,.1)
-        to (2.26,3)
+        to (2.26,2.2)
-        to [short, -*] (2.46,3)
+        to (.3, 2.2)
+        to [short, -*] (.3,3)
     
     (4.5,1.5) node[op amp] (oa) {}
     (fdoa.out -) to (oa.-)
@@ -39,6 +40,8 @@
 
     (5,0) node[ground]{} node[circ](4.5,0){}
 
+    (oa.up) to [short, -*] (4.46, 3)
+    (oa.down) to [short, -*] (4.46, 0)
     (oa.out) to [short,-] (5.5,1.5) node[right,draw=black] {MONITOR\_48I}
     
     ; 

tikz/mon48v.tex

@@ -25,10 +25,10 @@
         to [short, -*](1,0)
     (fdoa.up) 
         to (2.46,3)
-        to [short,*-o](6,3) node[right] {$V_{SS} = 3.3V$}
+        to [short,-o](6,3) node[right] {$V_{SS} = 3.3V$}
     (fdoa.up)+(-.2,.1)
         to (2.26,3)
-        to [short] (2.46,3)
+        to [short] (1,3)
     
     (4.5,1.5) node[op amp] (oa) {}
     (fdoa.out -) to (oa.-)
@@ -37,6 +37,8 @@
     (2.46,0) to [short,-o] (6,0) node[right]{GND}
     (5,0) node[ground]{} node[circ](4.5,0){}
 
+    (oa.up) to [short, -*] (4.46, 3)
+    (oa.down) to [short, -*] (4.46, 0)
     (oa.out) to [short,-] (5.5,1.5) node[right,draw=black] {MONITOR\_48V}
     ; 
 \end{circuitikz}

tikz/reticlepower.tex

@@ -5,15 +5,15 @@
 \begin{circuitikz}[scale=2]
 
     \draw[color=black, thick]
-    (0,2.8)
+    (0,3)
-        to [short, *-] (-.8,2.8)
+      to [short, *-] (-.8,3)
-        to [voltmeter] (-.8,-.35)
+      to [voltmeter] (-.8,-.5)
-        to [short, -*] (0,-.35)
+      to [short, -*] (0,-.5)
 
-    (0,3) 
+    (0,3.2)  node[right] {V$_\text{ss}$ = 1.8V}
-    to [R, l={$R_0$}, v_>=$I_{ges}$, o-] (0,1.5)
+      to [R, l={$R_0$}, v_>=$I_{ges}$, o-] (0,1.5)
       to [nos, *-] (0,1)
-      to [R, l={$R_1$}, v_>=$I_{ret}$, -o] (0,-.5)
+      to [R, l={$R_1$}, v_>=$I_{ret}$, -o] (0,-.7) node[right] {GND}
 
     (0,1.5)
       to [] (.6,1.5)

tikz/reticlepower_2.tex

@@ -5,15 +5,15 @@
 \begin{circuitikz}[scale=2]
 
     \draw[color=black, thick]
-    (0,2.8)
+    (0,3)
-        to [short, *-] (-.8,2.8)
+        to [short, *-] (-.8,3)
-        to [voltmeter] (-.8,-.35)
+        to [voltmeter] (-.8,-.5)
-        to [short, -*] (0,-.35)
+        to [short, -*] (0,-.5)
 
-    (0,3) 
+    (0,3.2) node[right] {V$_\text{SS}$ = 1.8V}
         to [R, l={$R_0$}, v_>=$I_{ges}$, o-] (0,1.5)
         to [nos, *-] (0,1)
-        to [R, l={$R_1$}, v_>=$I_{ret}$, -o] (0,-.5)
+        to [R, l={$R_1$}, v_>=$I_{ret}$, -o] (0,-.7) node[right] {GND}
 
     (0,1.5)
         to [R, l={$R_{0+}$}] (1,1.5)