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This thesis will provide a calibration of the PowerIt board as well as a regulation mechanism for its 1.8V power supplies.
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Calibration of this board, will provide more accurate measurements, and allow for later regulation of its 1.8V outputs.
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First its circuitry will be examined and their behavior tested, from which these circuits can be calibrated.
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With these calibrations a method for regulating both of its \SI{1.8}{\volt} power supplies will be implemented.
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First its circuitry will be examined and their behavior tested.
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Then the circuits can be calibrated.
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With these calibrations a method for regulating the main analog and digital power supplies will be implemented and verified on the Power wafer.
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This thesis also contains the changes done to the PowerIt firmware while working on these tasks.
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The new firmware now has a new protocol for communication over a I\(^2\)C.
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The new firmware now has a new protocol for communication over a I\(^2\)C connection.
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It can be used for accessing any calibration parameter or on board measurement.
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\end{abstract}
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\vspace{1cm}
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@ -23,23 +24,13 @@
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{\bfseries Zusammenfassung}
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\end{center}
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\begin{abstract}~\\
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Die Hauptaufgabe des PowerIts ist die Messung von und Versorgung mit verschiedenen Spannungen.
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Es versorgt alle Komponenten im BrainScaleS System des Humen Brain Projekts.
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Die Hauptaufgabe des PowerIts ist die Messung von, und Versorgung mit, verschiedenen Spannungen, die im BrainScaleS System des Humen Brain Projekts ben\"{o}tigt werden.
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Diese Arbeit liefert eine Kalibration des PowerIt, sowie eine Methode zur Regelung der \SI{1.8}{\volt} Spannungsausg\"{a}nge eines PowerIt.
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Zuerst werden daf\"{u}r die verbauten Schaltungen untersucht und auf ihr verhalten getestet und daraus k\"{o}nnen Kalibrationsdaten erfasst werden.
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Die sp\"{a}tere Regulierung der \SI{1.8}{\volt} Ausg\"{a}nge h\"{a}ngt dabei von der vorausgegangenen Kalibrierung ab.
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Diese Arbeit liefert eine Kalibration des PowerIt, sowie eine Methode zur Regelung der \SI{1.8}{\volt} Spannungsausg\"{a}nge.
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Zuerst werden daf\"{u}r die verbauten Schaltungen untersucht, auf ihr verhalten getestet und daraus Kalibrationsdaten erfasst.
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Die sp\"{a}tere Regulierung der haupt Analog- und Digitalspannungen h\"{a}ngt dabei von der vorausgegangenen Kalibrierung ab.
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Zus\"{a}tzlich enth\"{a}llt diese Arbeit die \"{A}nderungen, die an der Firmware vorgenommen worden sind, w\"{a}hrend diese Aufgaben bearbeitet wurden.
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Die neue Firmware enth\"{a}llt nun ein neues protocol f\"{u}r die Kommunikation \"{u}ber einen I\(^2\)C-Bus.
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Die neue Firmware enth\"{a}llt nun ein neues Protokoll f\"{u}r die Kommunikation \"{u}ber einen I\(^2\)C-Bus.
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Dieses Protokoll kann dazu genutzt werden auf beliebige Kalibrationsdaten oder Messwerde zuzugreifen.
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% Das akkurate Messen von und versorgen mit Spannungen ist ein integraler Teil jedweden elektrischen Systems, sodass diese reibungslos funktioniert.
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% Innerhalb des Bereiches des Human Brain Projektes, liefert diese Arbeit die Kalibration des BrainScaleS Teilsystems PowerIt, sowie die Regulierung einer Spannungsversorgung des BrainScaleS.
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%
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% Diese Arbeit verschafft einen Einblick in den internen Aufbau des PowerIt, dabei werden dessen Schaltungen untersucht und kalibriert, sodass diese in der \\System\"{u}berwachung nutzbar sind.
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% Ausserdem liefert diese Arbeit eine Methode der Regulation f\"{u}r eine der Spannungsversorgungen.
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% Diese basiert vor allem aif den Beobachtungen mittels eines experimentellen aufbaus eines in BrainScaleS genutzten Wafer Systems.
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%
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% Zus\"{a}tzlich enthalten sind die \"{A}nderungen, die an der PowerIt Firmware vorgenommen worden sind.
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% Dabei liegt der Fokus auf einem neuen Protokoll zur kommunikation, welches daf\"{u}r genutzt werden kann die Parameter und Werte der Kalibration und Regulation auszulesen oder zu setzen.
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\end{abstract}
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@ -1,38 +1,30 @@
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%! TEX root = ../thesis.tex
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\chapter{Appendix - Firmware}
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\section{Virtual Memory Mapping}
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THe biggest Change done to the Firmware was the implementation of a new communication protocol.
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This protocol uses the following table as reference
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The biggest change done to the firmware was the implementation of a new communication protocol.
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\begin{figure}
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\centering
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\input{./tabs/registerbuffer}
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\caption{}%
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\label{registerbuffer}
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\end{figure}
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\input{./tabs/registerbuffer}
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This protocol uses the table from \autoref{registerbuffer} as reference.
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\section{How to calibrate a PowerIt Board}
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The Calibration process is based on the PItSTOP Python scripts\footnote{
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% TODO: insert repo, and link to docs
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\href{https://acereca.ddns.net:11443/acereca/pitstop}{PItSTOP repository}
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}.
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These are split into \verb|server| and \verb|aggregator|. While the Server is handling the translation between raw I$^2$C data, and the JSON formatted result, the Aggregator takes this JSON and calculates a calibration.
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The calibration process is based on the PItSTOP python scripts.
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These are split into \verb|server| and \verb|aggregator|. While the server is handling the translation between raw I$^2$C data, and the JSON formatted result, the aggregator takes this JSON and calculates a calibration.
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Using the script any one of the following Values can be tested and calibrated:
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Using the script any one of the following values can be tested and calibrated:
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\begin{itemize}
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\item Input Voltage (\verb|pitstop.Aggregator.test_v_48()|)
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\item Input Current (\verb|pitstop.Aggregator.test_i_48()|)
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\item 9.6V Output Voltage (\verb|pitstop.Aggregator.test_v_10()|)
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\item 1.8V Output Voltage (\verb|pitstop.Aggregator.test_v_18()|)
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\item 1.8V Output Current (\verb|pitstop.Aggregator.test_i_18()|)
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\item input voltage (\verb|pitstop.Aggregator.test_v_48()|)
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\item input current (\verb|pitstop.Aggregator.test_i_48()|)
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\item 9.6V output voltage (\verb|pitstop.Aggregator.test_v_10()|)
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\item 1.8V output voltage (\verb|pitstop.Aggregator.test_v_18()|)
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\item 1.8V output current (\verb|pitstop.Aggregator.test_i_18()|)
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\end{itemize}
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\subsection{Setting up the Test Environment}
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The simplest way to setup an environment consists of cloning the PItSTOP project on a client:
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\begin{mintylst}{bash}
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> git clone https://url.to.pitstop
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> git clone ssh://git@gitviz.kip.uni-heidelberg.de/sw-stm32.git
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\end{mintylst}
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then substituting the \verb|rsync| target:
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@ -46,14 +38,14 @@ then substituting the \verb|rsync| target:
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\subsection{Running a Test}
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Running the test requires the following commands
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\\
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Serverside:
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serverside:
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\begin{mintylst}{bash}
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> python server.py
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\end{mintylst}
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Clientside:
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\end{mintylst}~\\
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clientside:
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\begin{mintylst}{bash}
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> python aggregator.py
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\end{mintylst}
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\end{mintylst}~\\
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Now just following the instructions given, the selected test can be run:
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\begin{mintylst}{text}
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Setting up calibration test for {}
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@ -65,7 +57,6 @@ Now just following the instructions given, the selected test can be run:
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Continue (y/N): y
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What is the Name given to the connected PowerIt? [Bxx]: B05
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\end{mintylst}
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\end{mintylst}~\\
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The result will consist of two diagrams one without calibration and one with.
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It will also write the newly obtained calibration data into \verb|pitdb.yaml|
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%! TEX root = ../thesis.tex
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\chapter{Experiments}
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Now that the theoretical model is complete, experiments can be done to start checking that model.
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The results of these experiments are usable for either voltage or current measurements.
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Now that the theoretical model is complete, experiments were done and the model checked.
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The results of these experiments are usable for either voltage or current calibration.
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\section{Experimental Setup}
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The first setup was used during the calibration phase, while the second setup was used for creating the regulation model.
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\subsection{Calibration Setup}
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To now calibrate a PowerIt a setup is required that can sweep the input voltage, as well as draw different currents from the PowerIt (see \autoref{fig:expsetup1}).
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To calibrate a PowerIt, a setup is required that can sweep the input voltage, as well as draw different currents from the PowerIt (see \autoref{fig:expsetup1}).
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For that a setup with a bench power supply an electronic load and an external voltmeter are used.
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Additionally a STM32-Discovery board and a RaspberryPi microcomputer were connected to flash new firmware onto the PowerIt.
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\begin{figure}[H]
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@ -38,7 +38,7 @@ The first setup was used during the calibration phase, while the second setup wa
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\includegraphics[height=.53\columnwidth]{pics/setup_pw_back_2.png}
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\caption{%
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Photographs of the second experimental setup.
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In this setup the Wafer system assembly was used.
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In this setup the wafer system assembly was used.
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This module has a height and length of 50cm and a width of 15cm.
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The left side shows the back side of the assembly.
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Here are the PowerIt (1), CURE (3) and AnaB (2) boards mounted, as well as a RaspberryPi (4) and a STM32-Discovery (5).
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@ -47,8 +47,7 @@ The first setup was used during the calibration phase, while the second setup wa
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\label{fig:expsetup2}
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\end{figure}
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This setup is similar to a BrainScaleS wafer module as it exists inside the system.
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But in contrast to these systems there are no FPGAs, AuxPwr or FCP boards (reference~\cite{waferembedding},fig 2.2).
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This setup is similar to a BrainScaleS wafer module as it exists inside the system, but in contrast to these systems there are no FPGAs, AuxPwr or FCP boards (reference~\cite{waferembedding},fig 2.2).
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The MainPCB has the PowerWafer attached and is also connected to 8 CURE boards, 2 AnaBs and a PowerIt.
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\section{Characterization}
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@ -60,20 +59,19 @@ For the complete calibration process the calibration setup was used.
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\subsection{Sampling Time}
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First up was selecting an optimal sample tick number.
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The sample ticks are the cycles for which an adc will probe a pin.
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In this case the uncalibrated measurement of input voltage was taken as example, and repeated with each of the possible 8 settings.
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In addition a voltage measurement was taken with an external voltmeter\footnote{Keithley 2100}. The voltameter was connected to the \SI{48}{\volt} input voltage terminal.
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The difference from the supplied Voltage, set with the external power supply\footnote{} was then calculated.
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In addition a voltage measurement was taken with an external voltmeter\footnote{Keithley 2100}. The voltmeter was connected to the \SI{48}{\volt} input voltage terminal.
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The difference from the supplied Voltage, set with the external power supply, was then calculated.
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In \autoref{sampleticks1} these calculated values are plotted.
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\begin{figure}
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\centering
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\hspace*{-.175\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./data/m04_cycledepends/cycledepends_20180529.pdf}
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\caption{Top: input difference from set voltage vs set voltage for different possible scaler values.
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Bottom: gain error of the linear fitted curves vs set scaler value (May 29th 2018, $\approx$32\si\degree C)}%
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\caption{Top: input voltage difference vs set voltage for different possible sampleTick values.
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Bottom: gain error of the linear fitted curves vs set scaler value.}%
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\label{sampleticks1}
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\end{figure}
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Also shown are the calculated gain errors, in case of all 8 settings.
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Important to note is the relative error in only one case not usable.
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Here the \verb|cycleTime|-Setting was set to 0 and therefore the smallest available sampling time of 3 Ticks was chosen.
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Here the \verb|cycleTime|-setting was set to 0 and therefore the smallest available sampling time of 3 ticks was chosen.
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This result excludes 0 as a possible value to use.
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All other measurements are within error margin of each other, and because a smaller time frame is preferred, the best value to use is 1.
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This results in a sample time of 15 Ticks or \SI{77}{\nano\second} per pin.
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\subsubsection{48V Input}
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In this setup the voltmeter is connected to positive and negative input voltage terminal.
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In this setup the voltmeter is connected to the positive and negative input voltage terminals.
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When looking at calibrating the input voltage (\autoref{v48_precalib}), we can clearly see a relatively constant offset of $\approx$1V.
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This is most likely the result of a offset voltage introduced behind the secondary amplifier.
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In \autoref{v48_precalib} a polynomial fit of 2nd degree\footnote{A Fit of second degree will be used in the complete calibration process} is done and its coefficients extracted (\autoref{pitdb}, line 9).
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These coefficients not only show an offset, but also some deviation in the incline and curve from the default values.
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These coefficients not only show an offset, but also some deviation in the incline and curve from the default values (\autoref{lst:pitdb-example}).
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\begin{figure}[H]
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\centering
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\vspace{-1cm}
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\caption{
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Calibration of \SI{48}{\volt} input voltage.
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Plotted are measured and reference vs the calculated vin voltage.
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The Calibration sweeps from \SIrange{43.2}{52.8}{\volt}.
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Plotted are measured and reference vs the calculated pin voltage.
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The calibration sweeps from \SIrange{43.2}{52.8}{\volt}.
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The fit is of second degree and its inverse are the to use calibration coefficients.
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(fit:{\(
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\pyval{poly48v2}V_\text{IN}^2+\pyval{poly48v1}V_\text{IN}+\pyval{poly48v0}=V_\text{MONITOR\_48V}
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@ -133,8 +131,8 @@ For the complete calibration process the calibration setup was used.
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For this setup the voltmeter was connected to a PowerIt \verb|GND| and \verb|10V| pad.
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The 9.6V Calibration, shows a slight difference between internal values and the reference measurement.
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This results in a list of coefficients (\autoref{pitdb}, line 7), very similar to those set in the theoretical defaults (\autoref{pitdb-example}).
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The 9.6V calibration, shows a slight difference between internal values and the reference measurement.
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This results in a list of coefficients (see \autoref{pitdb}, line 7), very similar to those set in the theoretical defaults (see \autoref{lst:pitdb-example}).
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\begin{figure}[H]
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\centering
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@ -144,7 +142,7 @@ For the complete calibration process the calibration setup was used.
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\vspace{-1cm}
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\caption{%
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Calibration of \SI{9.6}{\volt} input voltage.
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Plotted are measured and reference vs the calculated vin voltage.
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Plotted are measured and reference vs the calculated pin voltage.
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The Calibration sweeps from \SIrange{43.2}{52.8}{\volt}, and the supply modules divide that into \SIrange{8.64}{10.56}{\volt}.
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The fit is of second degree and its inverse are the to use calibration coefficients.
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(fit:{\(
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\label{v10_precalib}
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\end{figure}
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This small difference is explained by the simple voltage division used as our circuitry, and no amplification, as for the input voltage circuit.
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This small difference is explained by the simple voltage division used as our circuitry, and no amplification, like for the input voltage circuit.
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The residuals also show no systematic errors.
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\subsubsection{1.8V Output}
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The last voltage to calibrate is divided into two domains, one for supplying the analog, and one for the digital side of the wafer circuitry.
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Each deliver between \SI{1.549}{\volt} and \SI{2.022}{\volt} and both are settable by their respective circuit (both as in \autoref{fig:gen18v}).
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And for each measurement the voltmeter was either connected to POwerIt \verb|GND| and \verb|1.8V analog| or \verb|1.8V digital| pins.
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And for each measurement the voltmeter was either connected to PowerIt \verb|GND| and \verb|1.8V analog| or \verb|1.8V digital| pins.
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\begin{figure}[H]
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\centering
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\vspace{-1cm}
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\hspace*{-.15\columnwidth}
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\includegraphics[width=1.3\columnwidth]{./data/m03_poticalib/adccalib_02.pdf}
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\caption{Calibration: analog 1.8V Output voltage, plotted are external measurement and internal values vs set resistance R\(_S\)at the voltage module.}%
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\caption{Calibration of analog 1.8V output voltage, plotted are external measurement and internal values vs set resistance R\(_S\) at the voltage module.}%
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\label{fig:v18_precalib}
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\end{figure}
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\subsection{Currents}
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With now calibrated Voltages, the next step is to measure the behavior of the current measuring circuits.
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Note that the 9.6V Output does in fact not have a include circuit for measuring its current draw, and that this number will be obtainable from all other (calibrated) measurements.
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With now calibrated voltages, the next step is to observe the behavior of the current measuring circuits.
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Note that the 9.6V output does in fact not have a include circuit for measuring its current draw, and that this number will be obtainable from all other (calibrated) measurements.
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\subsubsection{48V Input}
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This experiment will calibrate the 48V input current.
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@ -194,7 +193,7 @@ For the complete calibration process the calibration setup was used.
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m_2 =&~\pyval{poly48i2}\nonumber
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\end{align}
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from which the inverse will used for calibration inside the PowerIt.
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from which the inverse will be used for calibration inside the PowerIt.
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\begin{figure}[H]
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\centering
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@ -213,8 +212,8 @@ For the complete calibration process the calibration setup was used.
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\subsubsection{1.8V Output}
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For the calibration experiment of both 1.8V output currents, the current draw ranged from \SIrange{0}{90}{\ampere}.
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The electric load was connected to a \verb|GND| and \verb|1.8V analog| or \verb|1.8V digital|pin depending on the measurement.
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For the calibration experiment of both 1.8V output currents, the current draw ranges from \SIrange{0}{90}{\ampere}.
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The electric load was connected to a \verb|GND| and \verb|1.8V analog| or \verb|1.8V digital| pin depending on the measurement.
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Observed were the values in \autoref{precalib18i}.
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Visible is a different incline of internal measurement and reference.
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m_2 =&~\pyval{poly18idigi2}\nonumber
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\end{align}
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This also show, that both parts are so similar in behavior, that a single sides observations would have sufficed.
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This also shows, that both parts are so similar in behavior, that a single sides observations would have sufficed.
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\section{1.8V Regulation}
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As Described beforehand the Output Voltages for both analog and digital can be adjusted to some degree and therefore we can compensate for the dropoff occurring between PowerIt Output Terminals and Reticles.
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As described beforehand the output voltages for both analog and digital can be adjusted to some degree and therefore we can compensate for the dropoff occurring between PowerIt output terminals and reticles.
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The following experiments were run unsing the Power Wafer setup.
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To run any test with the PowerWafer, the patterns in \autoref{fig:wpattern} were used.
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@ -269,18 +268,20 @@ Secondly, when powering Reticles all of the energy is converted into heat, via t
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\label{fig:wpattern}
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\end{figure}
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And although the copper heat sink and fans (see \autoref{fig:expsetup2}), should be able to handle this heat in a HICAN wafer system, when grouping together reticles and powering them, the dissipation does not suffice.
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And although the copper heat sink and fans (see \autoref{fig:expsetup2}), should be able to handle this heat in a HICANN wafer system, when grouping together reticles and powering them, the thermal conductivity does not suffice.
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This is the case, because the Power Wafer is drawing more current per reticle than a HICANN wafer would during an experiment.
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The internal temperature probes (between heat sink and wafer) register well above \SI{50}{\celsius}, when grouping 3 or more reticles.
|
||||
The observed overheating can be mitigated using the in \autoref{fig:wpattern} visualized patterns.
|
||||
|
||||
\subsection{Characterization of Dropoff}
|
||||
|
||||
Wanting to observe and characterize the voltage drop, first the connections between PowerIt and Reticles can be measured with the in \autoref{fig:retmodel} described connections, which in actuality are the PowerIT Terminal and corresponding analog readout pin on a Analog readout board.
|
||||
Wanting to observe and characterize the voltage drop, first the connections between PowerIt and reticles need to be measured with the in \autoref{fig:retmodel} described connections, which in actuality are the PowerIt terminal and corresponding analog readout pin on a AnaB.
|
||||
|
||||
To use the PowerWafer for testing one of the patterns in \autoref{fig:wpattern} will be used, each pattern has a approximate current draw of 120A and will distribute heat and draw per terminal evenly.
|
||||
To use the Power Wafer, one of the patterns in \autoref{fig:wpattern} will be used, each pattern has a approximate current draw of 120A and will distribute heat and draw per terminal evenly.
|
||||
|
||||
In \autoref{1v8dip} a single reticles (\#40) voltage drop for different Current Draws is visualized.
|
||||
A relatively linear trend and residuals of a trigonometric behavior can be observed (most likely the result of the inaccurately measurable current draw, which here is done inside the PowerIt).
|
||||
In \autoref{1v8dip} a single reticles (\#40) voltage drop for different current draws is visualized.
|
||||
A relatively linear trend can be observed.
|
||||
While the residuals look like the error could be systematic, with only 12 datapoints that is purely speculative.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -288,30 +289,30 @@ A relatively linear trend and residuals of a trigonometric behavior can be obser
|
|||
\hspace*{-.16\columnwidth}
|
||||
\includegraphics[width=1.3\columnwidth]{../pitstop/20180824/ret_vdip.pdf}
|
||||
\vspace{-1cm}
|
||||
\caption{Voltage drop observed between PowerIt and HICANN, each point represents a state after enabling additional Reticles on the PowerWafer (right upper wafer in \autoref{fig:wpattern})}
|
||||
\caption{Voltage drop observed between PowerIt and reticle \#40, each point represents a state after enabling additional Reticles on the PowerWafer (right upper wafer in \autoref{fig:wpattern})}
|
||||
\label{1v8dip}
|
||||
\end{figure}
|
||||
|
||||
Here a Voltage Drop vs. Current draw of the wafer shows a linear behavior and therefore can be regulated on basis of the current measurement done by on board Measurement circuit.
|
||||
Here a voltage drop vs. current draw of the wafer shows a linear behavior and therefore can be regulated on basis of the current measurement done by on board measurement circuitry.
|
||||
|
||||
\subsection{Numerical-Correction (Regulation)}
|
||||
|
||||
The initial idea, to approach the correction of this dropoff is a Numerical: the SWRM (\autoref{sec:swrm}) and its corresponding Equations can be applied here.
|
||||
\autoref{eq:fullreg}, which maps the measured output current to a corresponding potentiometer setting, requires the Dropoff to be linear, which was observed.
|
||||
The initial idea, to approach the correction of this dropoff is a numerical: the SWRM (\autoref{sec:swrm}) and its corresponding equations can be applied here.
|
||||
Equation~\ref{eq:fullreg}, which maps the measured output current to a corresponding potentiometer setting, requires the dropoff to be linear, which was observed.
|
||||
|
||||
To apply this approach, two assumptions need to be made:
|
||||
\begin{itemize}
|
||||
\item all reticles have the same current draw (already not accurate, see \autoref{1v8dip})
|
||||
\item all reticles experience the same voltage drop (as observed for reticle 40)
|
||||
\item all reticles experience the same voltage drop (as observed for reticle \#40)
|
||||
\end{itemize}
|
||||
|
||||
and the following four values are required, before a regulation can be attempted:
|
||||
\begin{itemize}
|
||||
\item \(I_{ret}\), the current draw of a single reticle,
|
||||
\item \(R_0\), the resistance between PowerIt and FET,
|
||||
\item \(R_1\), the resistance of a single Reticle
|
||||
\item \(R_1\), the resistance of the connection between FET and reticle
|
||||
|
||||
\item \(V_{off}\), the wanted Voltage at a Reticle
|
||||
\item \(V_{off}\), the desired voltage at a reticle (users choice)
|
||||
\end{itemize}
|
||||
|
||||
To get a representative value of \(I_{ret}\) for use in the SWRM, the mean current draw per reticle was taken (\autoref{fig:ihist}):
|
||||
|
|
@ -328,15 +329,15 @@ To get a representative value of \(I_{ret}\) for use in the SWRM, the mean curre
|
|||
\caption{Distribution of analog current draw for all reticles on the PowerWafer (which were possible to measure)}%
|
||||
\label{fig:ihist}
|
||||
\end{figure}
|
||||
The \autoref{fig:ihist} was obtained by measuring the increase in current draw for each reticle, for each of the 4 patterns (\autoref{fig:wpattern}).\\\\
|
||||
To obtain \(R_0\), the pattern in \autoref{fig:wafer-ret5} was used to take measurements for both the neighborhood as well as the farthest reticles.
|
||||
The \autoref{fig:ihist} was obtained by measuring the increase in current draw for each reticle and each of the 4 patterns (\autoref{fig:wpattern}).\\\\
|
||||
To obtain the limits of \(R_0\), the pattern in \autoref{fig:wafer-ret5} was used to take measurements for both the neighborhood as well as the farthest reticles.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\hspace*{.1\columnwidth}
|
||||
\includegraphics[width=.6\columnwidth]{../pitstop/processing/neighborhoood_5.pdf}
|
||||
\vspace{-1cm}
|
||||
\caption{Reticles used to determine correlation between distance and Voltage Drop}%
|
||||
\caption{Reticles used to determine correlation between distance and voltage drop}%
|
||||
\label{fig:wafer-ret5}
|
||||
\end{figure}
|
||||
|
||||
|
|
@ -345,11 +346,12 @@ To obtain \(R_0\), the pattern in \autoref{fig:wafer-ret5} was used to take meas
|
|||
\vspace*{-1cm}
|
||||
\hspace*{-.15\columnwidth}
|
||||
\includegraphics[width=1.3\columnwidth]{../pitstop/20180828/reticle_corr}
|
||||
\caption{Voltage drop vs current for both Reticles in direct neighborhood and farthest possible Reticles}%
|
||||
\caption{Voltage drop vs current for both reticles in direct neighborhood and farthest possible reticles}%
|
||||
\label{fig:ret5corr}
|
||||
\end{figure}
|
||||
|
||||
From \autoref{fig:ret5corr} it is possible to see that the distance between reticles that are used gives different behavior of the voltage drop. Both Inclines happen to be the extreme cases, while either being completely uncorrelated, the case for farthest Reticles, or being directly correlated by their distance, here observable for the neighboring Reticles.
|
||||
From \autoref{fig:ret5corr} it is possible to see that the distance between reticles that are used, gives different behavior of the voltage drop.
|
||||
Both inclines happen to be the extreme cases, while either being completely uncorrelated, the case for farthest Reticles, or being directly correlated by their distance, here observable for the neighboring Reticles.
|
||||
|
||||
Therefore we obtain two values for \(R_0\):
|
||||
|
||||
|
|
@ -367,7 +369,7 @@ from the same measurement it is also possible to extract \(R_1\) by extrapolatin
|
|||
|
||||
here the values obtained are within error margin of each other.
|
||||
|
||||
So applying these Values, the following behavior for regulation can be visualized:
|
||||
So applying these Values, the following behavior for regulation can be visualized.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -379,7 +381,7 @@ So applying these Values, the following behavior for regulation can be visualize
|
|||
|
||||
The in \autoref{fig:regswrm} visualized values show the theoretical \(P_{val}\) for the corresponding current.
|
||||
All of the dotted parts depict with this setup unachieveble values.
|
||||
This reaults in the PowerIts inability to correct for any change in current above a certain threshold.
|
||||
This results in the PowerIts inability to correct for any change in current above a certain threshold.
|
||||
In the domain above this threshold the resulting voltage would behave the same as before regulation.
|
||||
Note that the 1.8V regulation, should fail at about 80A of current draw.
|
||||
|
||||
|
|
@ -394,21 +396,24 @@ Now voltage drop per reticle, in a single reticle power state, was observed:
|
|||
\label{fig:vdiphist}
|
||||
\end{figure}
|
||||
|
||||
The histogram in \autoref{fig:vdiphist} has amean of
|
||||
The histogram in \autoref{fig:vdiphist} has a corrected mean of
|
||||
|
||||
\begin{align}
|
||||
\pyval{vdipmeancorr}
|
||||
\end{align}
|
||||
|
||||
\autoref{fig:wrdist} shows how those Voltages are Distributed over the complete PowerWafer.
|
||||
All white Reticles are not measurable, either because they were not functional or could not be read.
|
||||
The here obtained mean was taken without the in \autoref{fig:vdiphist} as red marked outliers.
|
||||
The reason beind that was that this model should apply for most cases and not include outliers as not to inflate the V\(_\text{drop}\) distribution range.
|
||||
|
||||
Figure~\ref{fig:wrdist} shows how those voltages are distributed over the complete PowerWafer.
|
||||
All white reticles are not measurable, either because they were not functional or could not be read.
|
||||
The occurances marked in red in \autoref{fig:vdiphist} are reticles \#11, \#20 and \#28, which were outliers and are excluded in the calculation of corrected values.
|
||||
|
||||
This results in a distribution, which when combined with the spread of \(R_0\) from \autoref{fig:ret5corr}, gives an approximate range for all reticles voltage drop at a given current draw (\autoref{fig:vrange}).
|
||||
This results in a distribution, which when combined with the spread of \(R_0\) from \autoref{fig:ret5corr}, gives an approximate range for all reticles voltage drop at a given current draw (\autoref{fig:reg}).
|
||||
|
||||
To be able to obtain the through AnaB pins measured voltages it should also be possible to use the CUREs voltage readout.
|
||||
The voltages obtained from these boards, should be comparable.
|
||||
THe reason for that is that we can assume a constand R\(_1\) for all reticles.
|
||||
The reason for that is that we can assume a constand R\(_1\) for all reticles.
|
||||
In \autoref{fig:vcure40} these voltages are visualized, in comparison to the AnaB voltages.
|
||||
|
||||
\begin{figure}[H]
|
||||
|
|
|
|||
|
|
@ -7,21 +7,21 @@
|
|||
|
||||
\section{The BrainScaleS System}
|
||||
|
||||
The BrainScaleS Wafer System which is visualized in \autoref{fig:wss}, developed and used in the electronic visions group at Heidelberg University is a neuromorphic hardware implementation~\cite{waferembedding}.
|
||||
On this Hardware, mixed-signal ASICs, or also called HICANNs, implement a behavior similar to that of a neuron found in biological systems.
|
||||
The BrainScaleS wafer system which is visualized in \autoref{fig:wss}, developed and used in the electronic visions group at Heidelberg University, is a neuromorphic hardware implementation~\cite{waferembedding}.
|
||||
On this hardware, mixed-signal ASICs, or also called HICANNs\footnote{High Input Count Analog Neural Network}, implement a behavior similar to that of a neuron found in biological systems.
|
||||
These ASIC chips are placed on a silicon wafer, and grouped into packs of 8, called reticles.
|
||||
With these Chips complex behavior of biological systems can be simulated.
|
||||
With these chips complex behaviors of biological systems can be simulated.
|
||||
|
||||
Focus of this thesis is part of the hardware implementation and only the following components will either be further examined or used later on:
|
||||
|
||||
\begin{itemize}
|
||||
\item Control Units for Reticles, short CURe boards
|
||||
\item Control Units for Reticles, short CURE boards
|
||||
|
||||
These boards control the power delivery mechanism for each of the 48 reticles.
|
||||
\item Analog Breakout boards, AnaB for short
|
||||
|
||||
Provided by these boards are direct connections to reticle voltages, two per reticle. These are normally shared between all 8 reticles.
|
||||
\item and power supply, called PowerIt.
|
||||
\item and its power supply, called PowerIt.
|
||||
\end{itemize}
|
||||
|
||||
\begin{figure}[H]
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
|
||||
\section{About the PowerIt Subsystem}
|
||||
|
||||
The main subject of this thesis is the PowerIt board, photographed in \autoref{fig:pitteststand}. It functions as power supply inside of the WaferScale system, described before, in which it provides e.g. the wafer with \SI{1.8}{\volt} and the FPGAs with \SI{9.6}{\volt}. Its maximum rated power draw is \SI{2}{\kilo\watt}.~\cite{poweritupgrade}
|
||||
The main subject of this thesis is the PowerIt board, photographed in \autoref{fig:pitteststand}. It functions as power supply inside of the wafer-scale system, described before, in which it provides e.g. the wafer with \SI{1.8}{\volt} and the FPGAs with \SI{9.6}{\volt}. Its maximum rated power draw is \SI{2}{\kilo\watt}.~\cite{poweritupgrade}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
|
|
@ -43,21 +43,25 @@
|
|||
\end{figure}
|
||||
|
||||
This PowerIt board has a integrated STM32 microcontroller\footnote{STM32F405RGT~\cite{stm32f405xx}} which runs a custom firmware based on ChibiOS~\cite{chibios}.
|
||||
The PowerIt also measures the following values:
|
||||
For this thesis import ant is, that the chip runs at \SI{169}{\mega\hertz}.
|
||||
Note that of its internal components mainly a 12bit ADC is used.
|
||||
It is clocked with the same internal frequency as the processor.
|
||||
|
||||
The PowerIt measures the following values via the STM32-internal ADC:
|
||||
|
||||
\begin{itemize}
|
||||
\item input voltage and current
|
||||
\item \SI{1.8}{\volt} output voltage and current each for analog and digital parts of the wafer circuits
|
||||
\item \SI{1.8}{\volt} output voltage and current each for analog and digital circuitry
|
||||
\item and the \SI{9.6}{\volt} output voltage
|
||||
\end{itemize}
|
||||
|
||||
which can then be used inside the firmware.
|
||||
which can then be used inside the firmware and read from devices via the I\(^2\)C connection.
|
||||
The external device can then get this information from the PowerIt to the BrainScaleS monitoring system.
|
||||
|
||||
The input voltage, nominal, is \SI{48}{\volt} and therefore the input current should not exceed \SI{41.7}{\ampere}
|
||||
Additionally the \SI{9.6}{\volt} are a set voltage obtained by the power supply modules\footnote{5:1 Bus converter IB0xxE096T48xx, 500W each}, which divide the input voltage by 5.
|
||||
Additionally the \SI{9.6}{\volt} are a set voltage obtained by the power supply modules\footnote{5:1 Bus converter IB0xxE096T48xx, 500W each~\cite{vicormods}} which divide the input voltage by 5.
|
||||
Lastly the \SI{1.8}{\volt} output voltage is variable.
|
||||
|
||||
|
||||
\newpage
|
||||
\section{Contents in Detail}
|
||||
|
||||
|
|
@ -67,12 +71,10 @@
|
|||
|
||||
Calibrating the PowerIt was the next task.
|
||||
The calibration characterizes the voltage measuring circuits, whose voltages are either coming into or leaving the PowerIt.
|
||||
Additionally there are a current measuring circuits for incoming current and both \SI{1.8}{\volt} output currents.
|
||||
A reference voltage measurement was used to generate a fitted polynomial.
|
||||
This polynomials coefficients are the calibration parameters used inside the PowerIt.
|
||||
Additionally there are current measuring circuits for incoming current and both \SI{1.8}{\volt} output currents.
|
||||
A reference voltage measurement was used to generate fitted polynomials.
|
||||
These polynomials coefficients are the calibration parameters used inside the PowerIt.
|
||||
|
||||
Taking these calibrations as basis, the \SI{1.8}{\volt} power supplies' behavior through different current draws could be observed.
|
||||
A simple model was generated from these measurements and applied.
|
||||
Also inside the formware a first iteration of that model was implemented and could now be tested.
|
||||
|
||||
This all resulted in the testing and quntification of the regulation mechanism, as well as a secondary model that could be used in the future.
|
||||
Also inmplemented inside the firmware was a first iteration of that model which could now be tested.
|
||||
|
|
@ -2,25 +2,35 @@
|
|||
|
||||
\chapter{Outlook}
|
||||
|
||||
All in all the set goals were achieved.
|
||||
|
||||
While all of the measurements could be calibrated they can still be fine tuned.
|
||||
As shown in \autoref{fig:postcalib10v}, the error of a calibrated measurement is not quite minimal.
|
||||
In the future it would be possible to make these even more accurate, either by using a different method for calculating, which is not based on second degree polynomials.
|
||||
Or by further calibration, as mentioned in the results chapter.
|
||||
The found accuracy was \(\approx\) \SI{.33}{\%}.
|
||||
To gain a better accuracy would require further iterations of the calibration process.
|
||||
In the future it should also be possible to make these even more accurate, either by using a different method than the internally used polynomial of second degree.
|
||||
This calculation could be of third degree or not even a polynomial.
|
||||
|
||||
The voltage distribution, as described in figures~\ref{fig:vdiphist} and~\ref{fig:wrdist}, was quantified and the SWRM could be used for creating a worst-case V\(_\text{drop}\) distribution as seen in \autoref{fig:reg}.
|
||||
Therefore a first iteration of a usable regulation mechanism could be implemented and verified (see \autoref{fig:postreg}).
|
||||
This mechanism allows for a certain degree of regulation until a current threshold is reached.
|
||||
This threshold was also agreeing with a beforehand calculated value of around \SI{80}{\ampere}
|
||||
The voltage distribution over the complete wafer was measured.
|
||||
Using this distribution and V\(_\text{drop}\)s behavior at different loads could then be combined with the first iteration regulation model (SWRM).
|
||||
This produced both the worst-case V\(_\text{drop}\) range as well as a set of formulas which could be used further.
|
||||
These formulas allowed for regulating the \SI{1.8}{\volt} terminals.
|
||||
Additionally a threshold current I\(_\text{thresh}\) could be observed.
|
||||
This current limits the regulation mechanism, and results in still usable, but unregulated V\(_\text{drop}\).
|
||||
This threshold current was also predictable with the theoretical considerations.
|
||||
To further develop this mechanism, another, more complex, model (DWRM) was proposed.
|
||||
The DWRM would allow for a more accurate regulation, which is specific to a given experiment and its chosen reticles.
|
||||
This model would narrow down the worst-case scenario depicted by figures~\ref{fig:reg} and~\ref{fig:postreg}.
|
||||
For that model to work, each experiment run on a HICANN wafer, would require a simulation of the distribution of voltage between the used reticles.
|
||||
This would minimize the maximum difference in voltage drop considerably.
|
||||
|
||||
For further developing this the more complex DWRM could be used.
|
||||
This would allow for a more accurate regulation, that would narrow down the worst-case scenario of \autoref{fig:reg}.
|
||||
For that model to work, each experiment run on a wafer, in the system, would require a simulation of the distribution of voltage between the used reticles.
|
||||
As to minimize the maximum difference in voltage drop.
|
||||
This could also factor in the number of active HICANNs per reticle.
|
||||
Furthermore the observed current threshold of \SI{81.3}{\ampere} is restricted by a internally used resistor value.
|
||||
If the minimum resistance of the \SI{1.8}{\volt} generating circuit were to be decreased, the threshold would increase.
|
||||
|
||||
Additionally the current threshold is restricted by the internally used resistor chain (described in \autoref{fig:gen18v}).
|
||||
If the minimum resistance of that circuit were to be changed, the threshold would move up in current.
|
||||
There are also external effects wich were not covered in this thesis.
|
||||
One of those is that all systems are subject to temperature changes and therefore might not be stable or noisy.
|
||||
Investigating this dependency would also allow for possible regulation mechanisms to compensate for changes in temperature.
|
||||
|
||||
Running a calibrated and regulating PowerIt inside a HICANN wafer system, would be the next step in testing the regulation mechanism.
|
||||
The now regulated voltages could be resulting in more stable experiments.
|
||||
It would also be feasable to now test the influence of different voltages on the wafers neuromorphic chips and their calculations.
|
||||
Additionally to run an experiment on a HICANN wafer, a calibration is needed, and could also be influenced by the now regulated \SI{1.8}{\volt} voltages.
|
||||
|
||||
|
||||
|
|
@ -20,7 +20,7 @@ The obtained calibration values for the in these experiments used PowerIt, are c
|
|||
PITDB entry for B05 PowerIt.
|
||||
\mintinline{cpp}{id} is obtained by the firmware and unique to each STM32Chip.
|
||||
The \mintinline{cpp}{name} corresponds to the label on each PowerIt.
|
||||
All \mintinline{cpp}{poly*} are all polynomial coefficients in order of 0th degree to 2nd degree.
|
||||
All \mintinline{cpp}{poly*} values are all polynomial coefficients in order of 0th degree to 2nd degree.
|
||||
}%
|
||||
\label{pitdb}
|
||||
\end{listing}
|
||||
|
|
@ -42,7 +42,7 @@ And to compare, the values in \autoref{lst:pitdb-example} are theoretical values
|
|||
\end{mintyfig}
|
||||
\codecaption{%
|
||||
Default PITDB entry for any PowerIt.
|
||||
All \mintinline{cpp}{poly*} are all polynomial coefficients in order of 0th degree to 2nd degree.
|
||||
All \mintinline{cpp}{poly*} values are all polynomial coefficients in order of 0th degree to 2nd degree.
|
||||
}%
|
||||
\label{lst:pitdb-example}
|
||||
\end{listing}
|
||||
|
|
@ -67,29 +67,28 @@ One example of a calibrated measurement can be seen in \autoref{fig:postcalib10v
|
|||
\end{figure}
|
||||
|
||||
This repeats the calibration measurement for \SI{9.6}{\volt}.
|
||||
Here quite similar values can be observed, with a maximum \(\Delta V\) of around \SI{31.7}{\milli\volt}.
|
||||
Here quite similar values can be observed, with a maximum \(\Delta V\) of around \SI{31.7}{\milli\volt} (\(\approx\) \SI{.33}{\%}).
|
||||
It is also possible to see a systematic error in \autoref{fig:postcalib10v}.
|
||||
This error could be corrected, but requires further iterations of the calibration procedure.
|
||||
Additional iterations would allow for a reduction of \(\Delta V\), up to a value of \SI{24.5}{\milli\volt} (\(\approx\) \SI{.25}{\%}).
|
||||
|
||||
%This result is similar to others, and for all it would be possible to achieve a bit better fits.
|
||||
In comparison to this, the \SI{1.8}{\volt} measurement should have a bit better accuracy because of the even simpler circuit.
|
||||
|
||||
\begin{align*}
|
||||
\SI{.33}{\%} \cdot \SI{1.8}{\volt} \approx \SI{5.9}{\milli\volt}\\
|
||||
\SI{.25}{\%} \cdot \SI{1.8}{\volt} \approx \SI{4.5}{\milli\volt}
|
||||
\end{align*}
|
||||
|
||||
And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\milli\volt}, again because of the circuits complexity.
|
||||
|
||||
\begin{align*}
|
||||
\SI{.33}{\%} \cdot \SI{48}{\volt} \approx \SI{158}{\milli\volt}\\
|
||||
\SI{.25}{\%} \cdot \SI{48}{\volt} \approx \SI{120}{\milli\volt}
|
||||
\end{align*}
|
||||
|
||||
%TODO: currents
|
||||
|
||||
\section{Regulation}\label{sec:withoutreg}
|
||||
|
||||
THese are the obtained results from attempting to regulate the \SI{1.8}{\volt} terminals.
|
||||
These are the obtained results from attempting to regulate the \SI{1.8}{\volt} terminals.
|
||||
|
||||
\subsection{Without Regulation}
|
||||
|
||||
|
|
@ -109,14 +108,14 @@ And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\
|
|||
\end{figure}
|
||||
|
||||
In \autoref{fig:reg} the expected spread of V\(_\text{drop}\) can be found.
|
||||
Thsi spread is the worst case scenario of V\(_\text{drop}\) distribution.
|
||||
The reason for that is that with a regulated voltage a constant V\(\text{drop}\) is expected.
|
||||
This spread is the worst case V\(_\text{drop}\) distribution.
|
||||
The reason for that is that with a regulated voltage a constant V\(_\text{drop}\) is expected.
|
||||
This applies to all currents up until \(\approx\) \SI{80}{\ampere}, becase from there the regulation would not work anymore and V\(_\text{drop}\) would behave like in the unregulated case.
|
||||
|
||||
\subsection{With Regulation}
|
||||
|
||||
To verify the regulation is working and to see if the prediction in \autoref{fig:regswrm} is correct new values were measured.
|
||||
These Values are the voltages with regulation enabled at different Reticles (see \autoref{fig:postreg}).
|
||||
These values are the voltages with regulation enabled at different reticles (see \autoref{fig:postreg}).
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -125,23 +124,23 @@ And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\
|
|||
\includegraphics[width=1.3\columnwidth]{../pitstop/20180828/ret_vdip.pdf}
|
||||
\vspace{-1cm}
|
||||
\caption{%
|
||||
Observed AnaB voltages after regulation at multiple reticles.
|
||||
Observed reticle voltages V\(_\text{ret}\) before or after regulation, at multiple reticles.
|
||||
Reticle \#40 shows the best-case scenario with the least amount of V\(_\text{drop}\).
|
||||
Reticle \#5 is a worst-case scenario, with the highest V\(_\text{drop}\) while still being a usable reticle.
|
||||
Reticle \#5 is a worst-case scenario, with the highest V\(_\text{drop}\) while still being placed central.
|
||||
}%
|
||||
\label{fig:postreg}
|
||||
\end{figure}
|
||||
|
||||
In \autoref{fig:postreg} three different reticles (\#5, \#29 and \#40) were measured.
|
||||
Observable is, that firstly the regulation, which was set to achieve \SI{1.8}{\volt} is working until I\(_{ana}\) is at I\(_\text{thresh}=\SI{80}{\ampere}\).
|
||||
Observable is, that firstly the regulation, which was set to achieve \SI{1.8}{\volt} is working until I\(_{ana}\) is at I\(_\text{thresh}=\SI{81.3}{\ampere}\).
|
||||
There the minmal potentiometer setting is used.
|
||||
From here V\(_\text{drop}\) behaves the same as without regulation.
|
||||
|
||||
Secondly the voltages for different reticles is different and not equal.
|
||||
Secondly V\(_\text{drop}\) for different reticles is different.
|
||||
This was one of the assumptions in the SWRM.
|
||||
To describe that behavior a distance based model (\autoref{sec:dwrm}: DWRM) could be the solution.
|
||||
|
||||
And third, under the assumption of a constant fit (up to I\(_{ana} \approx \SI{80}{\ampere}\)) a systematic error can be observed.
|
||||
The residuals observed are the result of the I\(_\text{ana}\) > I\(_\text{thresh}\) not regulated V\(_\text{drop}\).
|
||||
|
||||
Also, the expected behavior from \autoref{sec:withoutreg} can be observed.
|
||||
|
||||
|
|
@ -151,7 +150,7 @@ And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\
|
|||
\subsection{Distance Wafer Resistance Model (DWRM)}\label{sec:dwrm}
|
||||
|
||||
So far, the discussed measurements and SWRM have been enough to create a first iteration regulation mechanism.
|
||||
Until now assumptions like a constant R\(_0\) over the complete Wafer, have driven the creation of equations to satisfy this model.
|
||||
Until now assumptions like a constant R\(_0\) over the complete wafer, have driven the creation of equations to satisfy this model.
|
||||
They also led to observable inaccuracies, as seen in \autoref{eq:r0}.
|
||||
Although the SWRM approximates the real world, it is not exact enough.
|
||||
To further develop a model that could describe the real world setup in a better way, the next model would have to describe e.g. a different R\(_0\).
|
||||
|
|
@ -165,8 +164,8 @@ And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\
|
|||
\centering
|
||||
\includegraphics[width=.45\columnwidth]{tikz/reticlepower_2}
|
||||
\caption{Modified model of the to measure resistances and their currents.
|
||||
Similar to SWRM \(R_0\) describes the resistance of a connection between the PowerIt Output, up to the FET (depicted as switch), while \(R_1\) is a Resistance between FET and Reticles. But additionally \(R_{0+}\) described a Resistance, that depends on the distance between reticle and voltage connector.
|
||||
The measurement is done between output terminals on the PowerIt and pins on a Analog readout board}%
|
||||
Similar to SWRM \(R_0\) describes the resistance of the shortest connection between the PowerIt output, up to the FET (depicted as switch), while \(R_1\) is a resistance between FET and reticles. But additionally \(R_{0+}\) described a resistance, that depends on the distance between reticle and voltage connector.
|
||||
The measurement is done between output terminals on the PowerIt and pins on a AnaB.}%
|
||||
\label{fig:retmodelshell}
|
||||
\end{figure}
|
||||
|
||||
|
|
@ -176,7 +175,7 @@ And also the accuracy of measuring \SI{48}{\volt} should be worse than \SI{24}{\
|
|||
\centering
|
||||
\hspace*{-.14\columnwidth}
|
||||
\includegraphics[width=1.1\columnwidth]{../pitstop/20180821/reticel_rtheo.pdf}
|
||||
\vspace{-1cm}
|
||||
\caption{Distances of reticles to the nearest voltage supplying connection for DWRM, distance is in reticle-side length}%
|
||||
\vspace{-.5cm}
|
||||
\caption{Distances of reticles to the nearest voltage supplying connection for DWRM, distance is normed to the reticle-side length}%
|
||||
\label{fig:retmodelrdist}
|
||||
\end{figure}
|
||||
101
parts/theory.tex
101
parts/theory.tex
|
|
@ -1,21 +1,24 @@
|
|||
%! TEX root = ../thesis.tex
|
||||
\chapter{Theory}\label{ch:theory}
|
||||
This chapter will be discussing the principles used in the experiments.
|
||||
These will contain simplified circuits and their respective equations as well as component behavior as specified in their respective data sheets by their manufacturer
|
||||
These will contain simplified circuits and their respective equations as well as component behavior, specified in their respective data sheets.
|
||||
|
||||
\section{Hardware Component Behavior}
|
||||
|
||||
Before discussing the experimental results it needs to be clear what circuitry is used in these experiments and what behavior we expect.
|
||||
Keeping in mind, that these are theoretical values and will most likely not be exactly the same as those found in actual hardware, as all values given will always be within some error.
|
||||
Keeping in mind, that these are theoretical values and can be different from those found in actual hardware, as all given values will always be within some error.
|
||||
|
||||
Each of the three voltage regimes that will be observed on the PowerIt board, \SI{48}{\volt}, \SI{9.6}{\volt} and \SI{1.8}{\volt}, has a voltage- and in the cases of \SI{48}{\volt} and \SI{1.8}{\volt} also a current-measurement circuit.
|
||||
Each of the three voltage regimes that can be observed on the PowerIt board, \SI{48}{\volt}, \SI{9.6}{\volt} and \SI{1.8}{\volt}, has a voltage measurement circuit.
|
||||
In the cases of \SI{48}{\volt} and \SI{1.8}{\volt} there also exists a current measurement circuit.
|
||||
Additionally there is a temperature sensor built into the STM32 chip.
|
||||
|
||||
\subsection{ADC Calibration}\label{sec:adc}
|
||||
The measurements will be done by the STM32-Chip, which uses 12bit ADCs.
|
||||
The measurements will be done by a STM32-internal ADC.
|
||||
A single ADC will be switching between all connected pins.
|
||||
This Behavior can be problematic in regards to measuring accurately.
|
||||
The timing used to measure a single pin can be programmatically set from 3 up to 480 clock ticks\footnote{this clock is the internal adc clock, with a frequency of \SI{159}{\hertz}}
|
||||
The reason for that is that the switching process requires the voltage to change within a given number of cycles (sample ticks).
|
||||
The measured voltage would be dependent on the previous value if this sample time is not big enough.
|
||||
The timing used to measure a single pin can be set from 3 up to 480 clock ticks.
|
||||
|
||||
\subsection{48V Input Voltage}\label{sec:mon48v}
|
||||
|
||||
|
|
@ -23,21 +26,17 @@ These will contain simplified circuits and their respective equations as well as
|
|||
For voltage measurement the circuit needs to
|
||||
|
||||
\begin{itemize}
|
||||
\item divide our input voltage into a usable potential range
|
||||
\item decouple the input (\SI{48}{\volt}) from signal potential (\SI{3.3}{\volt})
|
||||
\item and amplify the voltage, to be in the STM32-Chips Voltage range of up to \SI{3.3}{\volt}.
|
||||
\item divide our input voltage into a usable potential range, which is accomplished with a 1:240 voltage divider,
|
||||
\item decouple the input (\SI{48}{\volt}) from signal potential (\SI{3.3}{\volt}), with a full differential operation amplifier
|
||||
\item and amplify the voltage, to be in the STM32-Chips Voltage range of up to \SI{3.3}{\volt}, with another amplifier, which also converts the differential into a single-ended signal.
|
||||
\end{itemize}
|
||||
|
||||
The already implemented circuit can be seen in \autoref{mon48v}.
|
||||
|
||||
It consists of a 1:240 voltage divider, a full differential isolation amplifier taking in the roughly \SI{200}{\milli\volt} (nominal voltage range), and amplifying it by a factor of 8 (\(r_\text{diffOpAmp}\)~\cite{diffopamp}).
|
||||
It is also decoupling the input and output voltages, so our \SI{48}{\volt} and \SI{3.3}{\volt} circuit parts are electrically insulated.
|
||||
The remaining operational amplifier provides difference to single ended conversion with an amplification or 1.1 (\(r_\text{OpAmp}\))
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=.9\textwidth]{./tikz/mon48v.pdf}
|
||||
\caption{Circuit for measuring the \SI{48}{\volt} input voltage, consisting of input potential (left), two resistors as voltage divider, one fully differential isolation amplifier (left), one operational Amplifier (right), output voltage as well as the connection to the STM32-Chips input pin (right)}%
|
||||
\caption{Circuit for measuring the \SI{48}{\volt} input voltage, consisting of input potential (left), two resistors as voltage divider, one fully differential isolation amplifier (left), one operational Amplifier (right), output voltage (right).}%
|
||||
\label{mon48v}
|
||||
\end{figure}
|
||||
|
||||
|
|
@ -48,11 +47,12 @@ These will contain simplified circuits and their respective equations as well as
|
|||
V_\text{48V in}\cdot\frac{R_1}{R_1+R_2} \cdot r_\text{diffOpAmp} \cdot r_\text{OpAmp} =&~V_\text{MONITOR\_48V}\nonumber\\
|
||||
\Leftrightarrow \quad \frac{V_\text{MONITOR\_48V}}{r_\text{diffOpAmp}\cdot r_\text{OpAmp}}\cdot\frac{R_1+R_2}{R_1} =&~V_\text{48V in}
|
||||
\intertext{and the extremes, when assuming \SI{48+-4.8}{\volt} are}
|
||||
V_\text{MONITOR\_48V, min} = \SI{43.2}{\volt}\cdot\frac{1}{240+1}\cdot 8\cdot 1.1 =&~\SI{1.5774}{\volt}\\
|
||||
V_\text{MONITOR\_48V, max} = \SI{52.8}{\volt}\cdot\frac{1}{240+1}\cdot 8\cdot 1.1 =&~\SI{1.9280}{\volt}
|
||||
V_\text{MONITOR\_48V, min} = \SI{43.2}{\volt}\cdot\frac{1}{240+1}\cdot 8\cdot 1.1 \approx&~\SI{1.6}{\volt}\\
|
||||
V_\text{MONITOR\_48V, max} = \SI{52.8}{\volt}\cdot\frac{1}{240+1}\cdot 8\cdot 1.1 \approx&~\SI{1.9}{\volt}
|
||||
\end{align}
|
||||
|
||||
The ADCs 12bit gives a maximum resolution of \SI{2.1}{\milli\volt}.
|
||||
The \SI{48+-4.8}{\volt} range was chosen under the assumption of a maximum \SI{10}{\%} error, for the power supply.
|
||||
The ADCs 12bit resolution gives a maximum voltage resolution of \(\approx\) \SI{2}{\milli\volt}.
|
||||
|
||||
\subsection{\SI{48}{\volt} Input Current}
|
||||
|
||||
|
|
@ -64,17 +64,18 @@ These will contain simplified circuits and their respective equations as well as
|
|||
\end{itemize}
|
||||
|
||||
To accomplish that, the circuit is measuring the voltage over a \SI{500}{\micro\ohm} shunt Resistor, while a current is flowing.
|
||||
By Ohms Law that results in a linear proportionality between current an the obtained voltage.
|
||||
Which is then decoupled and amplified by a factor of 8, as well as converted from a difference to single ended voltage, with a amplification factor of 1.1.
|
||||
The shunt resistor also produces about \SI{21}{\milli\watt} of heat at full current draw, which is easily dissipated.
|
||||
By Ohms Law that results in a linear proportionality between current and the obtained voltage, which is then decoupled and amplified by a factor of 8.
|
||||
It is also then converted from a differential to single ended voltage, with a amplification factor of 1.1.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=.9\textwidth]{./tikz/mon48i.pdf}
|
||||
\caption{Circuit for measuring the \SI{48}{\volt} input current, consisting of PowerIt, one shunt-resistor, one full diff isolating Amplifier, one operational amplifier, output potential, as well as the connection to the STM32-Chips input pin}%
|
||||
\caption{Circuit for measuring the \SI{48}{\volt} input current, consisting of PowerIt, one shunt-resistor, one full diff isolating Amplifier, one operational amplifier, output potential.}%
|
||||
\label{mon48i}
|
||||
\end{figure}
|
||||
|
||||
Here the same amplifiers as in \autoref{sec:mon48v} is used and so we can apply the following equation for our input current:
|
||||
Here the same amplifiers as in \autoref{sec:mon48v} are used and so we can apply the following equation for our input current:
|
||||
|
||||
\begin{align}
|
||||
I_\text{48V IN}\cdot R_\text{shunt} \cdot r_\text{diffOpAmp} \cdot r_\text{OpAmp} = V_\text{48I pin}\nonumber\\
|
||||
|
|
@ -84,14 +85,14 @@ These will contain simplified circuits and their respective equations as well as
|
|||
The current range is from \SI{0}{\ampere} up to \SI{41.7}{\ampere} (= \SI{2}{\kilo\watt} / \SI{48}{\volt})and gives a resulting observable voltage range from \SI{0}{\volt} to:
|
||||
|
||||
\begin{align}
|
||||
\SI{41.7}{\ampere}\cdot \SI{500}{\micro\ohm} \cdot 8\cdot 1.1 =& \SI{0.1833}{\volt}
|
||||
\SI{41.7}{\ampere}\cdot \SI{500}{\micro\ohm} \cdot 8\cdot 1.1 \approx&~\SI{185}{\milli\volt}
|
||||
\end{align}
|
||||
|
||||
This results in a maximum resolution of \SI{.18}{\ampere}.
|
||||
|
||||
\subsection{9.6V Output Voltage}
|
||||
The measurement of \SI{9.6}{\volt} is quite simpler.
|
||||
This Circuit consists of a 1:3 Voltage Divider.
|
||||
The measurement of \SI{9.6}{\volt} output voltage circuit is quite a bit simpler.
|
||||
This circuit consists of a 1:3 voltage divider.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -110,7 +111,7 @@ These will contain simplified circuits and their respective equations as well as
|
|||
to [short, *-] (3, 1) node[right, draw=black] {MONITOR\_10V};
|
||||
\end{circuitikz}
|
||||
}
|
||||
\caption{Circuit for measuring 9.6V output voltage. Consisting of a voltage divider with 1:4 ratio, input voltage (left) and output voltage (right)}%
|
||||
\caption{Circuit for measuring 9.6V output voltage. Consisting of a voltage divider with 1:3 ratio, input voltage (left) and output voltage (right)}%
|
||||
\label{fig:mon10v}
|
||||
\end{figure}
|
||||
|
||||
|
|
@ -120,17 +121,18 @@ These will contain simplified circuits and their respective equations as well as
|
|||
\Leftrightarrow \frac{V_\text{MONITOR\_10V}}{R_1} \cdot \left( R_1+R_2\right) =&~V_\text{9.6V IN}
|
||||
\end{align}
|
||||
|
||||
|
||||
With the given voltage range of the input voltage from \SIrange{43.2}{52.8}{\volt} the observable voltage range for this circuit is from \SIrange{8.64}{10.56}{\volt}.
|
||||
And with the 12bit ADC that gives a maximum resolution of \SI{3.2}{\milli\volt}
|
||||
|
||||
\subsection{1.8V Output Voltage}
|
||||
|
||||
This Voltage is measured directly with the STM32-Chip.
|
||||
This voltage is measured directly with the STM32-Chip.
|
||||
|
||||
Until now the voltages and currents could only be measured, now the mechanism for setting a resulting voltage at the \SI{1.8}{\volt} terminals is known.
|
||||
Until now the voltages and currents could only be measured, now the mechanism for setting a resulting voltage at the \SI{1.8}{\volt} terminals is changeable.
|
||||
The circuit for generating \SI{1.8}{\volt} can be seen in \autoref{fig:gen18v}.
|
||||
It consists of a power module and the three resistors R\(_\text{series}\), R\(_\text{parallel}\) and R\(_\text{pot}\).
|
||||
The resistances set the output to a given voltage of around \SI{1.8}{\volt}.
|
||||
Based on R\(_\text{pot}\) this voltage is varied, because resistance is settable via a digital potentiometer\footnote{MCP4152 digital potentiometer~\cite{mcp4152}}.
|
||||
Based on R\(_\text{pot}\) this voltage is varied, because this resistance is settable via a digital potentiometer\footnote{MCP4152 digital potentiometer~\cite{mcp4152}}.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -155,12 +157,12 @@ These will contain simplified circuits and their respective equations as well as
|
|||
Visualizing the \autoref{eq:rset} results in \autoref{fig:beh1v8}, in which the limits of this circuit are visible.
|
||||
|
||||
\begin{align}
|
||||
V_\text{MONITOR\_1V8, min} =&~\SI{1.549}{\volt}\\
|
||||
V_\text{MONITOR\_1V8, max} =&~\SI{2.022}{\volt}
|
||||
V_\text{MONITOR\_1V8, min} \approx&~\SI{1.6}{\volt}\\
|
||||
V_\text{MONITOR\_1V8, max} \approx&~\SI{2.0}{\volt}
|
||||
\end{align}
|
||||
|
||||
And these extremes will be a limiting factor later on.
|
||||
Also with 12bit ADCS that results in a maximum resolution of \SI{.8}{\milli\volt}.
|
||||
Also with the 12bit ADC that results in a maximum resolution of \(\approx\)\SI{1}{\milli\volt}.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
|
|
@ -170,8 +172,8 @@ These will contain simplified circuits and their respective equations as well as
|
|||
\caption{%
|
||||
Expected behavior curve of 1.8V output voltage vs potentiometer setting.
|
||||
Shown is the complete range of possible settings and their resulting voltage.
|
||||
The zoomed in partial view shows, that because the setting can only be of integer value any resulting values are also discrete.
|
||||
A single step can increase the voltage by somewhere between \SI{1.0545}{\milli\volt} and \SI{3.2500}{\milli\volt}
|
||||
The zoomed in partial view shows that because the setting can only be of integer value any resulting values are also discrete.
|
||||
A single step can increase the voltage by somewhere between \SI{1.1}{\milli\volt} and \SI{3.3}{\milli\volt}
|
||||
}%
|
||||
\label{fig:beh1v8}
|
||||
\end{figure}
|
||||
|
|
@ -198,17 +200,17 @@ These will contain simplified circuits and their respective equations as well as
|
|||
to [short, *-] (3, 1) node[right, draw=black] {VDD\_1V8\_*};
|
||||
\end{circuitikz}
|
||||
}
|
||||
\caption{Circuit for measuring 1.8V current. It features a ACS758 hall sensor, input voltage (left) and output voltage (right)}%
|
||||
\caption{Circuit for measuring 1.8V current. It features a ACS758 hall sensor, input current (left) and output voltage (right)}%
|
||||
\label{fig:mon18i}
|
||||
\end{figure}
|
||||
|
||||
The hall sensor is rated for a maximum constant current draw of 100A, and features the following behavior:
|
||||
The hall sensor is rated for a maximum constant current draw of \SI{200}{\ampere}, and features the following behavior:
|
||||
|
||||
\begin{align}
|
||||
I_\text{1.8V, in} \cdot \SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~V_\text{MONITOR\_1I8}\\
|
||||
\intertext{By applying the limits of \SI{0}{\ampere} and \SI{100}{\ampere}, the following voltage range can be observed:}
|
||||
\SI 0\ampere \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{0.12}{\volt}\\
|
||||
\SI{100}{\ampere} \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{0.52}{\volt}
|
||||
\intertext{By applying the limits of \SI{0}{\ampere} and \SI{200}{\ampere}, the following voltage range can be observed:}
|
||||
\SI 0\ampere \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{120}{\milli\volt}\\
|
||||
\SI{200}{\ampere} \cdot\SI{0.004}{\volt\per\ampere} + \SI{0.12}{\volt} =&~\SI{1040}{\milli\volt}
|
||||
\end{align}
|
||||
|
||||
These values and the used 12bit ADCs gives a maximum resolution of around \SI{.2}{\ampere}
|
||||
|
|
@ -216,8 +218,7 @@ These will contain simplified circuits and their respective equations as well as
|
|||
\section{1.8V Output Regulation}
|
||||
The method for regulating the \SI{1.8}{\volt} output voltage consists of two parts.
|
||||
|
||||
First the voltage, wanted at the output terminal and second the corresponding potentiometer setting to use for that voltage
|
||||
On the other hand, to calculate the voltage to output, it is necessary to classify the connections between the PowerIts output terminals and reticles.
|
||||
First the voltage, which is wanted at the output terminal and second the corresponding potentiometer setting to use for that voltage, on the other hand, to calculate the voltage to output, it is necessary to classify the connections between the PowerIts output terminals and reticles.
|
||||
|
||||
\subsection{Potentiometer Mapping}
|
||||
Combining Equations~\ref{eq:rpot},~\ref{eq:rset}, and~\ref{eq:vout}, we gather \autoref{eq:fullreg}. This equation maps a given output voltage to a corresponding potentiometer setting (reverse to \autoref{fig:beh1v8}).
|
||||
|
|
@ -231,12 +232,9 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
\frac{256}{10k\Omega}
|
||||
\end{align}
|
||||
|
||||
This mapping will be converted into a lookup table before the PowerIt firmware is initiated.
|
||||
|
||||
\subsection{Power Wafer}
|
||||
To test the \SI{1.8}{\volt} regulation the so called PowerWafer is going to be used.
|
||||
Its reticles can be controlled via the CURE board, similar to HICANN wafers, which are used in BrainScaleS.
|
||||
But the Power Wafer is different, as it cannot be used for any neuromorphic computation.
|
||||
Its reticles can be controlled via the CURE board, similar to HICANN wafers, which are used in BrainScaleS, but the Power Wafer is different, as it cannot be used for any neuromorphic computation.
|
||||
Its internals are ohmic resistors, which provide a maximum power draw per reticle of what is possible inside a usable wafer module.
|
||||
|
||||
% \begin{figure}[H]
|
||||
|
|
@ -246,11 +244,10 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
% \label{fig:wafer}
|
||||
% \end{figure}
|
||||
|
||||
It has the same layout as its system counterparts and each of the 48 reticles can be accessed, digitally as well as electrically.
|
||||
It has the same layout as its system counterparts and each of the 48 reticles can be accessed digitally, as well as electrically.
|
||||
|
||||
And like its system counterparts it is placed on a MainPCB (see \autoref{fig:mainpcb}).
|
||||
All CURE boards connect to it and control the PowerFETs, as well as provide voltage readout from each reticle.
|
||||
The CURE boards read right before \(R_1\) in \autoref{fig:retmodel}.
|
||||
|
||||
Also on the MainPCB are the AnaB boards.
|
||||
Note that here lies another specialization of the PowerWafer.
|
||||
|
|
@ -276,10 +273,10 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
|
||||
\subsection{Simple Wafer Resistance Model (SWRM)}\label{sec:swrm}
|
||||
|
||||
When powering any reticle on a wafer system, the voltage setting on the PowerIt side is set to about \SI{1.9}{\volt}.
|
||||
When powering any reticle on a wafer system, the voltage on the PowerIt side is set to about \SI{1.9}{\volt}.
|
||||
This then results in the reticles receiving around \SI{1.8}{\volt}.
|
||||
Additionally when running experiments on a HICANN wafer, the current draw results in a drop of this received voltage.
|
||||
This behavior is most likely the result of a resistance between power supply and reticles.
|
||||
This behavior is the result of a resistance between power supply and reticles.
|
||||
|
||||
To describe the resistances on such a wafer module, a model can be used.
|
||||
This model combines all resistances introduced through any connection point between supply terminal (copper pad on PowerIt) and PowerFET into R\(_0\).
|
||||
|
|
@ -292,8 +289,8 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
\centering
|
||||
\includegraphics[width=.4\columnwidth]{./tikz/reticlepower.pdf}
|
||||
\caption{
|
||||
Model of the to measure resistances and their currents, \(R_0\) describes the resistance of a connection between the PowerIt Output and up to the FET (depicted as switch), while \(R_1\) is a Resistance between FET and Reticles.
|
||||
The measurement is done between Output Terminals on the PowerIt and pins on a Analog readout board.
|
||||
SWRM circuit containing the to measure resistances and their currents. \(R_0\) describes the resistance of a connection between the PowerIt output and up to the FET (depicted as switch), while \(R_1\) is a resistance between FET and Reticles.
|
||||
The measurement is done between on the PowerIt and pins on a AnaB.
|
||||
}%
|
||||
\label{fig:retmodel}
|
||||
\end{figure}
|
||||
|
|
@ -308,7 +305,7 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
I_{ges} = n_{ret} \cdot I_{ret}
|
||||
\end{align}
|
||||
|
||||
Therefore the voltage drop \(V_\text{drop}\) as measured by a voltmeter (see \autoref{fig:retmodel}) can be described with \autoref{eq:vdip}
|
||||
Therefore the voltage drop \(V_\text{drop}\) as measured by a voltmeter (connected as in \autoref{fig:retmodel}) can be described with \autoref{eq:vdip}
|
||||
|
||||
\begin{align} \label{eq:vdip}
|
||||
V_\text{drop} =&\ V_{R_1} + V_{R_0} \nonumber\\
|
||||
|
|
@ -322,4 +319,4 @@ On the other hand, to calculate the voltage to output, it is necessary to classi
|
|||
\Rightarrow V_O =& I_\text{ret} \cdot \left( R_1 + R_0 \cdot n_\text{ret} \right) + V_\text{off}\label{eq:vout2}
|
||||
\end{align}
|
||||
|
||||
In equations~\ref{eq:voff} and~\ref{eq:vout2} reference the desired voltage at reticle level V\(\text{off}\) and the voltage at a PowerIt terminal V\(_O\).
|
||||
Equations~\ref{eq:voff} and~\ref{eq:vout2} reference the desired voltage at reticle level V\(\text{off}\) and the voltage at a PowerIt terminal V\(_O\).
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
\makeatletter
|
||||
\begin{titlepage}
|
||||
\begin{center}
|
||||
\Large\textbf{Department of Physics and Astronomy\\
|
||||
|
|
@ -9,7 +10,7 @@ University of Heidelberg}
|
|||
Bachelor Thesis in Physics\\
|
||||
submitted by\\
|
||||
\vspace{0.5cm}
|
||||
\Large\textbf{Patrick Nisblé}\\
|
||||
\Large\textbf{\@author}\\
|
||||
\normalsize
|
||||
\vspace{0.5cm}
|
||||
born in Mannheim (Germany)\\
|
||||
|
|
@ -22,19 +23,19 @@ born in Mannheim (Germany)\\
|
|||
\newpage
|
||||
|
||||
|
||||
|
||||
\huge\textbf{Calibration of BrainScaleS PowerIt Subsystem and Regulating a BrainScaleS Power Supply}
|
||||
\huge\textbf{\@title}
|
||||
|
||||
\vspace{17cm}
|
||||
|
||||
\normalsize
|
||||
This Bachelor Thesis has been carried out by Patrick Nisblé at the\\
|
||||
This Bachelor Thesis has been carried out by \@author{} at the\\
|
||||
Electronic Visions Group\\
|
||||
Kirchhoff Institute for Physics\\
|
||||
Ruprecht-Karls-Universität Heidelberg\\
|
||||
under the supervision of\\
|
||||
Prof. Dr. Karlheinz Meier
|
||||
Prof.\ Dr.\ Karlheinz Meier
|
||||
|
||||
\vfill
|
||||
\end{center}
|
||||
\end{titlepage}
|
||||
\makeatother
|
||||
BIN
thesis.pdf
BIN
thesis.pdf
Binary file not shown.
|
|
@ -29,7 +29,7 @@
|
|||
\providecommand*{\listingautorefname}{code}
|
||||
|
||||
\author{Patrick Nisblé}
|
||||
\title{\color{myteal}Calibration and Regulation of PowerIt Hardware}
|
||||
\title{Calibration and Regulation on BrainScaleS PowerIt Board}
|
||||
\begin{document}
|
||||
%\maketitle
|
||||
\pagenumbering{Roman}
|
||||
|
|
|
|||
BIN
tikz/mon48i.pdf
BIN
tikz/mon48i.pdf
Binary file not shown.
|
|
@ -15,14 +15,14 @@
|
|||
(1,3) to [short, -*] (1,2.52)
|
||||
(1,3) to [short, -*] (.52, 3)
|
||||
|
||||
(0,0) node[left]{GND$_{V_{IN}}$} to [short, o-] (1,0)
|
||||
(0,0) node[left]{GND$_{-48V}$} to [short, o-] (1,0)
|
||||
|
||||
(2.5,1.5) node[fd op amp] (fdoa) {}
|
||||
(fdoa.+) to [short,-*] (1,1.0)
|
||||
(fdoa.-) to [short,-*] (1,2.0)
|
||||
(fdoa.down)
|
||||
to (2.46,0)
|
||||
to [short,-o] (6,0) node[right]{GND}
|
||||
to [short,-o] (6,0) node[right]{GND$_{3.3V}$}
|
||||
(fdoa.down)+(-.2,-.1)
|
||||
to (2.26,0)
|
||||
to [short, -*](1,0)
|
||||
|
|
|
|||
BIN
tikz/mon48v.pdf
BIN
tikz/mon48v.pdf
Binary file not shown.
|
|
@ -14,7 +14,7 @@
|
|||
to [R, text width=1cm, l={R2\\240k}, *-] (1,1.5)
|
||||
to [R, text width=1cm, l={R1 1k}, *-] (1,0)
|
||||
|
||||
(0,0) node[left]{$GND_{V_{IN}}$}
|
||||
(0,0) node[left]{GND$_{-48V}$}
|
||||
to [short, o-] (1,0)
|
||||
|
||||
(fdoa.+) to (1,1.5)
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
(fdoa.out -) to (oa.-)
|
||||
(fdoa.out +) to (oa.+)
|
||||
|
||||
(2.46,0) to [short,-o] (6,0) node[right]{GND}
|
||||
(2.46,0) to [short,-o] (6,0) node[right]{GND$_{3.3V}$}
|
||||
(5,0) node[ground]{} node[circ](4.5,0){}
|
||||
|
||||
(oa.up) to [short, -*] (4.46, 3)
|
||||
|
|
|
|||
Loading…
Reference in New Issue