%! TEX root = ../thesis.tex
\chapter{Experiments}
<contains the experimental observations defined in th theory>

\section{Characterization}

\subsection{sampling time}
The first experiment needed to run was selecting an optimal number of cycles for which the adc will probe the to it at that moment connected pin. 

The ADC Sampling works by connecting one of the internal 12bit ADCs to a given Pin and then taking a sample value and disconnecting from the Pin, this proceure repeats fo all given pins and is bound to a Timer, whose Interrupts define the number of Ticks an ADC has to process the connected Voltage on a Pin.

In this case the uncalibrated measurement of our input voltage was taken as example, and repeated with each of the possible 8 settings of the in Firmware used value.

The resulting errors can be seen in figures \ref{sampleticks1} and \ref{sampleticks2}

\begin{figure}[H]
    \centering
    \hspace*{-.16\columnwidth}
    \includegraphics[width=1.3\columnwidth]{./data/m04_cycledepends/cycledepends_20180529.pdf}
    \caption{plotted difference from set input voltage, and fitted linearly, May 29th 2018, $\approx$32\si\degree C}
    \label{sampleticks1}
\end{figure}

Both figures \ref{sampleticks1} and \ref{sampleticks2} contain the relative error of the measured voltage compared to the theoretical , set input voltages. therefore the reference measurements (yellow), taken with an external multimeter, are not at 0.
Also shown are the calculated gain erors which would need to be corrected for in case of all 8 settings.
Important in figure \ref{sampleticks1} is the relative error in only the 0th case, here the cycleTime-Setting was set to 0 and therefore the smallest available sampletime. All other measurements are within errormargin of each other. 
The secondary plots confirm the 
\begin{figure}[H]
    \centering
    \hspace*{-.16\columnwidth}
    \includegraphics[width=1.3\columnwidth]{./data/m04_cycledepends/cycledepends_20180530.pdf}
    \caption{plotted difference from set input voltage, and fitted linearly, May 30th 2018, $\approx$25\si\degree C}
    \label{sampleticks2}
\end{figure}

\subsection{Voltages}

    These Measuremts are expected to be relatively inaccurate, the more components are contained in their respective measurement circuit.

    \subsubsection{48V Input}

    \begin{figure}[H]
        \centering
        \hspace*{-.16\columnwidth}
        \includegraphics[width=1.3\columnwidth]{../pitstop/20180621/v48.pdf}
        \caption{TODOF}
        \label{v48_precalib}
    \end{figure}

    When looking at calibrating the input voltage (fig. \ref{v48_precalib}), we can clearly see a relatively constand offset of $\approx$1V which can be the influence of inaccurate voltage division and later amplification. The resulting calibrated polnomial coefficients (fig. \ref{pitdb}, line 8) are show not only a offset, but also some deviation in the incline and curve of our polynomial fit.

    \subsubsection{9.6V Output}
    \begin{figure}[H]
        \centering
        \hspace*{-.16\columnwidth}
        \includegraphics[width=1.3\columnwidth]{../pitstop/20180706/v10_0_nocalib.pdf}
        \caption{TODOF}
        \label{v10_precalib}
    \end{figure}

    The 9.6V Calibration shows only a slight deviation of the internal values and the reference measurement, which results in a list of coefficients (fig. \ref{pitdb}, line 7), very similar to those set in the theoretical defaults.

    \begin{align}
        \sigma_{9.6V} = %TODO%
    \end{align}

    this difference is explained by the simple voltage division used for our circuitry, and no amplification, as seen in the circuit for input voltage.

    \subsubsection{1.8V Output}

        %\begin{figure}[H]
        %    \centering
        %    \hspace*{-.16\columnwidth}
        %    \includegraphics[width=1.3\columnwidth]{./data/m02_adccalib_48/adccalib_v18ana.pdf}
        %    \caption{}
        %    \label{1v8anabefore}
        %\end{figure}
        %\begin{figure}[h]
        %    \centering
        %    \hspace*{-.16\columnwidth}
        %    \includegraphics[width=1.3\columnwidth]{./data/m02_adccalib_48/adccalib_v18digi.pdf}
        %    \caption{}
        %    \label{1v8digibefore}
        %\end{figure}

    \begin{figure}[H]
        \centering
        \hspace*{-.06\columnwidth}
        \includegraphics[width=1.1\columnwidth]{./data/m03_poticalib/adccalib_02-eps-converted-to.pdf}
        %\includegraphics[width=1.\columnwidth]{./pitstop/20180702/i18ana_nocalib.pdf}
        %\includegraphics[width=1.\columnwidth]{./pitstop/20180702/i18digi_nocalib.pdf}
        \caption{TODOF}
        \label{v18_precalib}
    \end{figure}


\subsection{Currents}

    \subsubsection{48V Input}

        %TODO: 19.6 and 20.6 unusable
        % \begin{figure}[h]
        %     \centering
        %     \includegraphics[width=\textwidth]{../pitstop/20180619/i48.pdf}
        %     \caption{Calibration of input current adcs 19.06.2018}
        %     \label{}
        % \end{figure}
        % \begin{figure}[h]
        %     \centering
        %     \hspace*{-.16\columnwidth}
        %     \includegraphics[width=1.3\columnwidth]{../pitstop/20180620/i48.pdf}
        %     \caption{Calibration of input current adcs 20.06.2018}
        %     \label{}
        % \end{figure}
        \begin{figure}[H]
            \centering
            \hspace*{-.16\columnwidth}
            \includegraphics[width=1.3\columnwidth]{pitstop/20180621/i48.pdf}
            \caption{Calibration of input current adcs 21.06.2018}
            \label{}
        \end{figure}

    \subsubsection{9.6V Output}

    \subsubsection{1.8V Output}
        \begin{figure}[H]
            \centering
            %\hspace*{-.16\columnwidth}
            \vspace*{-.02\paperheight}
            \includegraphics[width=\columnwidth]{pitstop/20180702/i18ana_nocalib.pdf}
            \includegraphics[width=\columnwidth]{pitstop/20180702/i18digi_nocalib.pdf}
            \caption{Pre Calibration Measurement of Output Current at the 1.8V Analog Terminal (2.7.2018)}
            \label{precalib18iana}
        \end{figure}


\section{after Calibration}

\minty[minted options={lastline=10}, label={pitdb}]{yaml}{./pitstop/pitdb.yaml}

\subsection{Voltages}

    \subsubsection{48V Input}

    \subsubsection{9.6V Output}

    \subsubsection{1.8V Output}

\subsection{Currents}

    \subsubsection{48V Input}

    \subsubsection{9.6V Output}

    \subsubsection{1.8V Output}
        \begin{figure}[H]
            \centering
            \hspace*{-.16\columnwidth}
            \includegraphics[width=1.3\columnwidth]{../pitstop/20180702/i18ana_postcalib.pdf}
            \caption{Post Calibration Measurement of Output Current at the 1.8V Analog Terminal (29.06.2018}
            \label{postcalib18iana}
        \end{figure}

\section{1.8V Regulation}

\subsection{Characterization of Dropoff}

Wanting to observe and characterize the voltage drop, happening between the PowerIt output terminal and the HICANN Chips, first the in figure \ref{1v8dip} monitored behavior can be seen.

\begin{figure}[H]
    \centering
    \hspace*{-.16\columnwidth}
    \includegraphics[width=1.3\columnwidth]{../pitstop/20180727/ret_vdip.pdf}
    \caption{Voltage dip observed between PowerIt and HICANN, each point represents the state after enabling additional Reticles on the PowerWafer}
    \label{1v8dip}
\end{figure}

\subsection{after Numerical-Correction}

The initial approach is a numerical. Through derivation from figures \ref{1v8dip} and \ref{v18_precalib} we can plot a function which maps the measured output current to a corresponding potentiometer setting (fig. \ref{numericalreg}) for which the observed dropoff will be mitigated (or at least near that). Also important is that it is not possible to use non interger values for the potentiometer setting.

\begin{figure}[H]
    \centering
    \hspace*{-.16\columnwidth}
    \includegraphics[width=1.3\columnwidth]{../pitstop/20180727/ret_regulation.pdf}
    \caption{Potentiometer Setting (discrete integer), derived from ouput current (discrete floating point). }
    \label{numericalreg}
\end{figure}

Fitting these values, with a polynomial of 2nd degree, we obtain:
\begin{align}
    P_{val} =& \lfloor m_2 \cdot I_{ana}^2 + m_1 \cdot I_{ana} + m_0 \rceil\\
    m_2 =& 51.390262 \frac 1 A\\ 
    m_1 =& -0.263850\frac 1 A\nonumber\\
    m_0 =& 0.000258\frac 1 A\nonumber
\end{align}

Which is the numeraical solution if the only desired voltage on HICAN Chips is 1.8V. But if we want to change these, we need a more general solution.

Assuming the 2nd order Term to be small enough, we can assume a linear proportionality between the current and voltage:

\begin{align}
I_{ana, eff} = I_{ana} - \frac{V_{out}-1.8V}{c}
\end{align}

where c is obtained from the linear fit (incline) in figure \ref{1v8dip}

\begin{align}
    c = 71.6978\cdot 10^{-3} \frac V A
\end{align}

\section{Pitfalls}

