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add transparen figs, update 201800815 1630

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acereca 2018-08-15 16:25:25 +02:00
parent 10fb660a9a
commit 83af3672fd
14 changed files with 59 additions and 64 deletions
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data/m03_poticalib/adccalib_02.pdf
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data/m03_poticalib/processing_poticalib.py
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@ -55,8 +55,7 @@ plt.plot(
plt.xlabel('$R_{BCU,Set}$/k$\Omega$')
plt.ylabel('V$_{1V8A}$/V')
plt.title("PowerIt Calibration: Analog Potentiometer")
plt.legend()
#-plt.savefig("2kw_direct.png")
plt.savefig("adccalib_{:02d}.pdf".format(lognum))
plt.savefig("adccalib_{:02d}.pdf".format(lognum), transparent=True)

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data/theory/i48.pdf
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data/theory/mktheory.py
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@ -1,10 +1,12 @@
import matplotlib.pyplot as plt
import numpy as np
import wafer
import VisTools.plotting as vtp
import VisTools.tex as vtt
plt.style.use('bmh')
plt.rcParams['axes.facecolor'] = 'white'
plt.figure(figsize=(8, 3))
plt.figure(figsize=(8, 4))
def gen_reticle_empty():
@ -54,9 +56,17 @@ def gen_1v8_theory():
ydata = 30100 / (ydata + 6490) * .7 + .7
plt.clf()
plt.plot(xdata, ydata)
plt.plot(xdata, ydata, label="Equation after Datasheet")
plt.xlabel("Potentiometer Setting")
vps = vtp.fit(xdata, ydata, lambda x,m,p,a,c: a/(m*x-p)+c, [.1, -1, 1, 1.5])
#plt.plot(xdata, vps[2].n / (vps[0].n * xdata - vps[1].n) + vps[3].n)
vtt.unc_tolatex(vps[0], None, 'theo.tex', name="m")
vtt.unc_tolatex(vps[1], None, 'theo.tex', name="p")
vtt.unc_tolatex(vps[2], None, 'theo.tex', name="a")
vtt.unc_tolatex(vps[3], None, 'theo.tex', name="c")
plt.xlabel("Potentiometer Setting P$_{val}$")
plt.ylabel("V$_{1.8V out}$")
plt.savefig('v18.pdf')

10
data/theory/theo.tex Normal file
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@ -0,0 +1,10 @@
\ExplSyntaxOn
\newcommand{\pyval}[1]{%
\str_case:nn{#1}{%
{ 0 }{ m = \SI{-1.6911+-0.0000}{ }}
{ 1 }{ p = \SI{567.6618+-0.0000}{ }}
{ 2 }{ a = \SI{-621.1199+-0.0000}{ }}
{ 3 }{ c = \SI{0.9318+-0.0000}{ }}
}
}
\ExplSyntaxOff

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data/theory/v18.pdf
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71
parts/experiments.tex
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@ -1,17 +1,18 @@
%! TEX root = ../thesis.tex
\chapter{Experiments}
<contains the experimental observations defined in th theory>
Now that the theoretical model exists, it can be checked with experiments.
\section{Characterization}
Now the Experiments to run, are those characterizing the behavior of the used hardware. These values can then later used for calibrating a PowerIt.
\subsection{sampling time}
The first experiment needed to run was selecting an optimal number of cycles for which the adc will probe the to it at that moment connected pin.
First up was selecting an optimal number of cycles for which the adc will probe the to it at that moment connected pin, like described in \autoref{sec:adc}
The ADC Sampling works by connecting one of the internal 12bit ADCs to a given Pin and then taking a sample value and disconnecting from the Pin, this proceure repeats fo all given pins and is bound to a Timer, whose Interrupts define the number of Ticks an ADC has to process the connected Voltage on a Pin.
In this case the uncalibrated measurement of input voltage was taken as example, and repeated with each of the possible 8 settings.
In this case the uncalibrated measurement of our input voltage was taken as example, and repeated with each of the possible 8 settings of the in Firmware used value.
The resulting errors can be seen in figures \ref{sampleticks1} and \ref{sampleticks2}
To be able to compare a reference voltage was measured with an external Voltmeter.
The resulting errors, from the set Voltage, can be seen in figures \ref{sampleticks1} and \ref{sampleticks2}
\begin{figure}[H]
\centering
@ -21,10 +22,10 @@ The resulting errors can be seen in figures \ref{sampleticks1} and \ref{sampleti
\label{sampleticks1}
\end{figure}
Both figures \ref{sampleticks1} and \ref{sampleticks2} contain the relative error of the measured voltage compared to the theoretical , set input voltages. therefore the reference measurements (yellow), taken with an external multimeter, are not at 0.
Also shown are the calculated gain erors which would need to be corrected for in case of all 8 settings.
Important in figure \ref{sampleticks1} is the relative error in only the 0th case, here the cycleTime-Setting was set to 0 and therefore the smallest available sampletime. All other measurements are within errormargin of each other.
The secondary plots confirm the
Both figures \ref{sampleticks1} and \ref{sampleticks2} contain the relative error of the measured voltage compared to the theoretical ,set input voltages. therefore the reference measurements (yellow), taken with an external multimeter, are not at 0.
Also shown are the calculated gain erors, which would need to be corrected for, in case of all 8 settings.
Important to note is the relative error in only the 0th case (both Figures), here the cycleTime-Setting was set to 0 and therefore the smallest available sampletimeof 3 Ticks. This excludes 0 a possible value to use. All other measurements are within errormargin of each other, and therefore the best candidate is a value of 1 resulting in a measuretime of 15 Ticks.
\begin{figure}[H]
\centering
\hspace*{-.175\columnwidth}
@ -33,27 +34,31 @@ The secondary plots confirm the
\label{sampleticks2}
\end{figure}
Lastly the difference in disribution of measured values in both Figures, shows a Temperature dependency of the noisy data measured by the ADC.
\subsection{Voltages}
These Measuremts are expected to be relatively inaccurate, the more components are contained in their respective measurement circuit.
These Measuremts are expected to be less accurate, the more components are contained in their respective measurement circuit. Because small errors will accumulate and in the case of 48V's be amplified.
\subsubsection{48V Input}
\begin{figure}[H]
\centering
\vspace{-1cm}
\hspace*{-.16\columnwidth}
\includegraphics[width=1.3\columnwidth]{./pitstop/20180809/calib_V48.pdf}
\caption{TODOF}
\includegraphics[width=1.3\columnwidth]{../pitstop/20180815/calib_v48.pdf}
\caption{Calibration of input voltage, plotted are a external measurement and internal values, vs the recalculated pin voltage based on the internal value and used default function (coefficients see \autoref{pitdb-example})}%
\label{v48_precalib}
\end{figure}
When looking at calibrating the input voltage (fig. \ref{v48_precalib}), we can clearly see a relatively constand offset of $\approx$1V which can be the influence of inaccurate voltage division and later amplification. The resulting calibrated polnomial coefficients (fig. \ref{pitdb}, line 8) are show not only a offset, but also some deviation in the incline and curve of our polynomial fit.
When looking at calibrating the input voltage (fig. \ref{v48_precalib}), we can clearly see a relatively constand offset of $\approx$1V which can be the influence of an inaccurate resistor inside the voltage division and later amplification. The resulting calibrated polnomial coefficients (see \autoref{pitdb}, line 8) not only show an offset, but also some deviation in the incline and curve of our polynomial fit of 2nd degree (A Fit of second degree will be used in the complete calibration process).
\subsubsection{9.6V Output}
\begin{figure}[H]
\centering
\vspace{-1cm}
\hspace*{-.16\columnwidth}
\includegraphics[width=1.3\columnwidth]{./pitstop/20180809/calib_v10.pdf}
\includegraphics[width=1.3\columnwidth]{../pitstop/20180815/calib_v10.pdf}
\caption{TODOF}
\label{v10_precalib}
\end{figure}
@ -61,33 +66,19 @@ The secondary plots confirm the
The 9.6V Calibration shows only a slight deviation of the internal values and the reference measurement, which results in a list of coefficients (fig. \ref{pitdb}, line 7), very similar to those set in the theoretical defaults.
\begin{align}
\sigma_{9.6V} = %TODO%
\sigma_{9.6V} \approx 5.3\%
\end{align}
this difference is explained by the simple voltage division used for our circuitry, and no amplification, as seen in the circuit for input voltage.
\subsubsection{1.8V Output}
%\begin{figure}[H]
% \centering
% \hspace*{-.16\columnwidth}
% \includegraphics[width=1.3\columnwidth]{./data/m02_adccalib_48/adccalib_v18ana.pdf}
% \caption{}
% \label{1v8anabefore}
%\end{figure}
%\begin{figure}[h]
% \centering
% \hspace*{-.16\columnwidth}
% \includegraphics[width=1.3\columnwidth]{./data/m02_adccalib_48/adccalib_v18digi.pdf}
% \caption{}
% \label{1v8digibefore}
%\end{figure}
\begin{figure}[H]
\centering
\vspace{-1cm}
\hspace*{-.15\columnwidth}
\includegraphics[width=1.3\columnwidth]{./data/m03_poticalib/adccalib_02.pdf}
\caption{TODOF}
\caption{TODOF}%
\label{fig:v18_precalib}
\end{figure}
@ -95,24 +86,10 @@ The secondary plots confirm the
\subsection{Currents}
\subsubsection{48V Input}
%TODO: 19.6 and 20.6 unusable
% \begin{figure}[h]
% \centering
% \includegraphics[width=\textwidth]{./pitstop/20180619/i48.pdf}
% \caption{Calibration of input current adcs 19.06.2018}
% \label{}
% \end{figure}
% \begin{figure}[h]
% \centering
% \hspace*{-.16\columnwidth}
% \includegraphics[width=1.3\columnwidth]{./pitstop/20180620/i48.pdf}
% \caption{Calibration of input current adcs 20.06.2018}
% \label{}
% \end{figure}
\begin{figure}[H]
\centering
\hspace*{-.16\columnwidth}
%TODO: transparent
\includegraphics[width=1.3\columnwidth]{./pitstop/20180809/calib_i48.pdf}
\caption{Calibration of input current adcs 21.06.2018}
\label{}

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parts/intro.tex
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@ -5,9 +5,8 @@
\section{What is the BrainScale System?}
The BrainScale Wafer System~\cite{hbpguidebook}, developed and used in the electronic visions Group at Heidelberg University is a neuromorhic hardware implementation.\\
For this thesis only some core components are important:
The BrainScale Wafer System~\cite{hbpguidebook}, developed and used in the electronic visions Group at Heidelberg University is a neuromorhic hardware implementation.\\\\
For this thesis the following core components are of importantance:
\begin{itemize}
\item the mixed-signal ASICs, named HICANNs, structured in packs of 8 into ``Reticles''
\item the Control Units for Reticles, short CURE Boards

2
parts/results.tex
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@ -52,7 +52,7 @@ An example entry for each PowerIt entry looks like figure \ref{pitdb-example}
poly18v: [0.0, 1.0, 0.0]
poly48v: [0.0, 27.386, 0.0]
\end{mintyfig}
\end{mintyfig}%
\end{figure}

12
parts/theory.tex
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@ -107,7 +107,7 @@ This equation is in contrast to all previous behavior models not of a linear nat
\centering
\hspace*{-.165\textwidth}
\includegraphics[width=1.3\textwidth]{./data/theory/v18.pdf}
\caption{Expected bahavior of our output voltage by setting the potentiometer}%
\caption{Expected behavior of our output voltage by setting the potentiometer}%
\label{fig:beh1v8}
\end{figure}
\subsection{1.8V Output Current}
@ -128,10 +128,10 @@ The circuit for measuring current is also quite straight forward. It consists of
to [short, o-] (1,2)
to [] (1,1.5)
(1.2,1) node[draw=black, regular polygon, regular polygon sides=4, minimum size=2.7cm]{amc}
(1.2,1) node[draw=black, regular polygon, regular polygon sides=4, minimum size=2.7cm]{acs758}
(1.7,1)
to [short, *-] (3, 1) node[right, draw=black] {VDD\_1V8\_};
to [short, *-] (3, 1) node[right, draw=black] {VDD\_1V8\_*};
\end{circuitikz}
}
@ -143,7 +143,7 @@ As mentioned beforehand, the actual hardware will differ in behavior from its th
To calibrate these readouts we need to employ some simple actions.
\subsection{serial ADC readout}
\subsection{serial ADC readout}\label{sec:adc}
While the measurements done by the STM32-Chip are using a 12bit ADC, there are not enough of these inside the chip to be able to completely parallelize the measurements, so only one ADC will be switching between all connected pins. This Behavior can be problematic in regards to measuring accurately. The timing used to measure a single line can be programmatically set from 3 up to 480 clock ticks\footnote{this clock is the internal adc clock, with a frequency of }
\section{1.8V Output Regulation}
@ -234,7 +234,7 @@ With this model the voltage is now expected to change depending on the reticles
\begin{figure}[H]
\centering
\includegraphics[width=\columnwidth]{./pitstop/20180809/reticel_rtheo.pdf}
\caption{Distances of reticles to the nearest voltage suppling connection for DWRM, distance is in reticle-side length}%
\includegraphics[width=\columnwidth]{../pitstop/20180815/reticel_rtheo.pdf}
\caption{Distances of reticles to the nearest voltage supplying connection for DWRM, distance is in reticle-side length}%
\label{fig:retmodelrdist}
\end{figure}

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pitstop

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Subproject commit 96ce7ad09137308b55b4d5d427178d514ab99e07
Subproject commit a85618419a1d4f7a91179745f68488c2acb1e32a

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ubib

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Subproject commit 479a79f96a7e2262c98959f0291948ee3639ed51
Subproject commit 07fefcff6dd652c93c9907d10511fe5ef6001320